Changeset 61013bd in mainline


Ignore:
Timestamp:
2011-09-24T17:03:27Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
7d5057e
Parents:
9dd79bc7
Message:

sb16: Fix register offsets.

Location:
uspace/drv/audio/sb16
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/audio/sb16/registers.h

    r9dd79bc7 r61013bd  
    4343        ioport8_t mixer_address;
    4444        ioport8_t mixer_data;
    45         ioport16_t dsp_reset;
     45        ioport8_t dsp_reset;
     46        ioport8_t __reserved1; /* 0x7 */
    4647        ioport8_t fm_address_status2;
    4748        ioport8_t fm_data2;
    4849        ioport8_t dsp_data_read;
     50        ioport8_t __reserved2; /*0xb*/
    4951        ioport8_t dsp_write; /* Both command and data, bit 7 is write status */
    5052#define DSP_WRITE_READY (1 << 7)
     53        ioport8_t __reserved3; /*0xd*/
    5154        ioport8_t dsp_read_status; /* Bit 7 */
    5255#define DSP_READ_READY (1 << 7)
    53         ioport8_t reserved;
     56        ioport8_t __reserved4; /*0xf*/
    5457        ioport8_t cd_command_data;
    5558        ioport8_t cd_status;
  • uspace/drv/audio/sb16/sb16.c

    r9dd79bc7 r61013bd  
    4545        pio_write_8(&drv->regs->dsp_write, command);
    4646}
    47 
     47/*----------------------------------------------------------------------------*/
    4848static inline uint8_t sb16_dsp_read(sb16_drv_t *drv)
    4949{
     
    5555        return pio_read_8(&drv->regs->dsp_data_read);
    5656}
    57 
    58 
     57/*----------------------------------------------------------------------------*/
    5958/* ISA interrupts should be edge-triggered so there should be no need for
    6059 * irq code magic */
     
    7978
    8079        /* Reset DSP, see Chapter 2 of Sound Blaster HW programming guide */
    81         pio_write_16(&drv->regs->dsp_reset, 1);
     80        pio_write_8(&drv->regs->dsp_reset, 1);
    8281        udelay(3);
    83         pio_write_16(&drv->regs->dsp_reset, 0);
     82        pio_write_8(&drv->regs->dsp_reset, 0);
    8483        udelay(100);
    8584
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