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Changeset 5e761f3 in mainline


Ignore:
Timestamp:
2013-01-24T20:21:18Z (9 years ago)
Author:
Maurizio Lombardi <m.lombardi85@…>
Branches:
lfn, master
Children:
b1011dae
Parents:
b7e41ac
Message:

boot mm.c fixes:

  • disable the MMU before starting changing the page table content.
  • invalidate the TLB entries before turning the MMU on.
  • remove dead code.
File:
1 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/mm.c

    rb7e41ac r5e761f3  
    3737#include <arch/asm.h>
    3838#include <arch/mm.h>
     39
     40/** Disable the MMU */
     41static void disable_paging(void)
     42{
     43        asm volatile (
     44                "mrc p15, 0, r0, c1, c0, 0\n"
     45                "bic r0, r0, #1\n"
     46                "mcr p15, 0, r0, c1, c0, 0\n"
     47        );
     48}
    3949
    4050/** Check if caching can be enabled for a given memory section.
     
    100110                init_ptl0_section(&boot_pt[page], page);
    101111       
    102         /*
    103          * Create 1:1 virtual-physical mapping in kernel space
    104          * (upper 2 GB), physical addresses start from 0.
    105          */
    106         /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
    107          * thus mapping only lower 2GB is not not enough.
    108          * Map entire AS 1:1 instead and hope it works. */
    109         for (page = split_page; page < PTL0_ENTRIES; page++)
    110 #ifndef MACHINE_beagleboardxm
    111                 init_ptl0_section(&boot_pt[page], page - split_page);
    112 #else
    113                 init_ptl0_section(&boot_pt[page], page);
    114 #endif
    115        
    116112        asm volatile (
    117113                "mcr p15, 0, %[pt], c2, c0, 0\n"
     
    129125                "ldr r0, =0x55555555\n"
    130126                "mcr p15, 0, r0, c3, c0, 0\n"
    131                
    132 #ifdef PROCESSOR_armv7_a
    133                 /* Read Auxiliary control register */
    134                 "mrc p15, 0, r0, c1, c0, 1\n"
    135                 /* Mask to enable L2 cache */
    136                 "ldr r1, =0x00000002\n"
    137                 "orr r0, r0, r1\n"
    138                 /* Store Auxiliary control register */
    139                 "mrc p15, 0, r0, c1, c0, 1\n"
    140 #endif
     127
    141128                /* Current settings */
    142129                "mrc p15, 0, r0, c1, c0, 0\n"
     
    156143#endif
    157144                "orr r0, r0, r1\n"
     145
     146                /* Flush the TLB */
     147                "mcr p15, 0, r0, c8, c7, 0\n"
    158148               
    159                 /* Store settings */
     149                /* Store settings, enable the MMU */
    160150                "mcr p15, 0, r0, c1, c0, 0\n"
    161151                ::: "r0", "r1"
     
    165155/** Start the MMU - initialize page table and enable paging. */
    166156void mmu_start() {
     157        disable_paging();
    167158        init_boot_pt();
    168159        enable_paging();
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