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Changeset 45f4f19 in mainline


Ignore:
Timestamp:
2012-03-05T20:33:48Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
1b90e90
Parents:
d1ca752
Message:

ohci: Use different macros for register and memory access.

Location:
uspace/drv/bus/usb/ohci/hw_struct
Files:
1 added
4 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.c

    rd1ca752 r45f4f19  
    5858                /* Mark as dead, used for dummy EDs at the beginning of
    5959                 * endpoint lists. */
    60                 OHCI_WR(instance->status, ED_STATUS_K_FLAG);
     60                OHCI_MEM32_WR(instance->status, ED_STATUS_K_FLAG);
    6161                return;
    6262        }
     
    6565
    6666        /* Status: address, endpoint nr, direction mask and max packet size. */
    67         OHCI_WR(instance->status,
     67        OHCI_MEM32_WR(instance->status,
    6868            ((ep->address & ED_STATUS_FA_MASK) << ED_STATUS_FA_SHIFT)
    6969            | ((ep->endpoint & ED_STATUS_EN_MASK) << ED_STATUS_EN_SHIFT)
     
    7474        /* Low speed flag */
    7575        if (ep->speed == USB_SPEED_LOW)
    76                 OHCI_SET(instance->status, ED_STATUS_S_FLAG);
     76                OHCI_MEM32_SET(instance->status, ED_STATUS_S_FLAG);
    7777
    7878        /* Isochronous format flag */
    7979        if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS)
    80                 OHCI_SET(instance->status, ED_STATUS_F_FLAG);
     80                OHCI_MEM32_SET(instance->status, ED_STATUS_F_FLAG);
    8181
    8282        /* Set TD to the list */
    8383        const uintptr_t pa = addr_to_phys(td);
    84         OHCI_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK);
    85         OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
     84        OHCI_MEM32_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK);
     85        OHCI_MEM32_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
    8686
    8787        /* Set toggle bit */
    8888        if (ep->toggle)
    89                 OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
     89                OHCI_MEM32_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
    9090
    9191}
  • uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h

    rd1ca752 r45f4f19  
    4040#include <usb/host/endpoint.h>
    4141
    42 #include "../ohci_regs.h"
    4342#include "../utils/malloc32.h"
    4443#include "transfer_descriptor.h"
    4544
    4645#include "completion_codes.h"
     46#include "mem_access.h"
    4747
    4848/**
     
    117117{
    118118        assert(instance);
    119         return (OHCI_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG)
    120             || (OHCI_RD(instance->status) & ED_STATUS_K_FLAG);
     119        return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG)
     120            || (OHCI_MEM32_RD(instance->status) & ED_STATUS_K_FLAG);
    121121}
    122122
     
    124124{
    125125        assert(instance);
    126         OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
     126        OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
    127127}
    128128
     
    135135{
    136136        assert(instance);
    137         return (OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK)
    138             != (OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK);
     137        return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK)
     138            != (OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK);
    139139}
    140140
     
    148148        assert(instance);
    149149        const uintptr_t pa = addr_to_phys(td);
    150         OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
     150        OHCI_MEM32_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
    151151}
    152152
     
    154154{
    155155        assert(instance);
    156         return OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK;
     156        return OHCI_MEM32_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK;
    157157}
    158158
     
    160160{
    161161        assert(instance);
    162         return OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK;
     162        return OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_PTR_MASK;
    163163}
    164164
     
    174174        const uint32_t pa = addr_to_phys(next);
    175175        assert((pa & ED_NEXT_PTR_MASK) << ED_NEXT_PTR_SHIFT == pa);
    176         OHCI_WR(instance->next, pa);
     176        OHCI_MEM32_WR(instance->next, pa);
    177177}
    178178
     
    180180{
    181181        assert(instance);
    182         return OHCI_RD(instance->next) & ED_NEXT_PTR_MASK;
     182        return OHCI_MEM32_RD(instance->next) & ED_NEXT_PTR_MASK;
    183183}
    184184
     
    191191{
    192192        assert(instance);
    193         return (OHCI_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0;
     193        return (OHCI_MEM32_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0;
    194194}
    195195
     
    203203        assert(instance);
    204204        if (toggle) {
    205                 OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
     205                OHCI_MEM32_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
    206206        } else {
    207207                /* Clear halted flag when reseting toggle TODO: Why? */
    208                 OHCI_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
    209                 OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
     208                OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
     209                OHCI_MEM32_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
    210210        }
    211211}
  • uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.c

    rd1ca752 r45f4f19  
    6060        bzero(instance, sizeof(td_t));
    6161        /* Set PID and Error code */
    62         OHCI_WR(instance->status,
     62        OHCI_MEM32_WR(instance->status,
    6363            ((dir[direction] & TD_STATUS_DP_MASK) << TD_STATUS_DP_SHIFT)
    6464            | ((CC_NOACCESS2 & TD_STATUS_CC_MASK) << TD_STATUS_CC_SHIFT));
     
    6666        if (toggle == 0 || toggle == 1) {
    6767                /* Set explicit toggle bit */
    68                 OHCI_SET(instance->status, TD_STATUS_T_USE_TD_FLAG);
    69                 OHCI_SET(instance->status, toggle ? TD_STATUS_T_FLAG : 0);
     68                OHCI_MEM32_SET(instance->status, TD_STATUS_T_USE_TD_FLAG);
     69                OHCI_MEM32_SET(instance->status, toggle ? TD_STATUS_T_FLAG : 0);
    7070        }
    7171
    7272        /* Alow less data on input. */
    7373        if (dir == USB_DIRECTION_IN) {
    74                 OHCI_SET(instance->status, TD_STATUS_ROUND_FLAG);
     74                OHCI_MEM32_SET(instance->status, TD_STATUS_ROUND_FLAG);
    7575        }
    7676
    7777        if (buffer != NULL) {
    7878                assert(size != 0);
    79                 OHCI_WR(instance->cbp, addr_to_phys(buffer));
    80                 OHCI_WR(instance->be, addr_to_phys(buffer + size - 1));
     79                OHCI_MEM32_WR(instance->cbp, addr_to_phys(buffer));
     80                OHCI_MEM32_WR(instance->be, addr_to_phys(buffer + size - 1));
    8181        }
    8282
    83         OHCI_WR(instance->next, addr_to_phys(next) & TD_NEXT_PTR_MASK);
     83        OHCI_MEM32_WR(instance->next, addr_to_phys(next) & TD_NEXT_PTR_MASK);
    8484
    8585}
  • uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.h

    rd1ca752 r45f4f19  
    3838#include <stdint.h>
    3939
    40 #include "../ohci_regs.h"
     40#include "mem_access.h"
    4141#include "completion_codes.h"
    4242
     
    100100{
    101101        assert(instance);
    102         const int cc =(OHCI_RD(instance->status)
     102        const int cc =(OHCI_MEM32_RD(instance->status)
    103103            >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;
    104104        /* This value is changed on transfer completion,
     
    119119{
    120120        assert(instance);
    121         const int cc = (OHCI_RD(instance->status)
     121        const int cc = (OHCI_MEM32_RD(instance->status)
    122122            >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;
    123123        return cc_to_rc(cc);
     
    136136                return 0;
    137137        /* Buffer end points to the last byte of transfer buffer, so add 1 */
    138         return OHCI_RD(instance->be) - OHCI_RD(instance->cbp) + 1;
     138        return OHCI_MEM32_RD(instance->be) - OHCI_MEM32_RD(instance->cbp) + 1;
    139139}
    140140#endif
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