Changeset 3156582 in mainline


Ignore:
Timestamp:
2005-09-11T12:48:42Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8e3fb24c
Parents:
8491c48
Message:

Updated symtab so that it works correctly with BE architectures.
Changed compiler for BE MIPS to be mips-sgi-irix5, because
mipsel -EB does not behave correctly.
Doc updates to amd64.
Added ARC BIOS support to MIPS architecture. Putchar works correctly,
kernel passed FPU & some rwlock tests.

Files:
3 added
22 edited
1 moved

Legend:

Unmodified
Added
Removed

  • arch/amd64/_link.ld.in

    r8491c48 r3156582  
    6363        _hardcoded_kernel_size = (ktext_end - ktext_start) + (unmapped_ktext_end - unmapped_ktext_start) + (kdata_end - kdata_start) + (unmapped_kdata_end - unmapped_kdata_start);
    6464
     65        /* Symbols that need to be accessed both from real mode & long mode */
     66        /* e820*_boot is real mode (pre-above-1MB-move), e820* is */
     67        /* kernel mapped above-1MB-physical copied symbol */
    6568        e820table_boot = KA2PA(e820table) - BOOT_OFFSET;
    6669        e820counter_boot = KA2PA(e820counter) - BOOT_OFFSET;
     70
     71        /* real_bootstrap_gdtr is mapped real_bootstrap_gdtr_boot */
     72        /* It is physically outside of kernel area, we have to access */
     73        /* it after modification from long mode for booting */
     74        /* SMP slave processors */
    6775        real_bootstrap_gdtr = PA2KA(real_bootstrap_gdtr_boot);
    6876}

  • arch/amd64/include/byteorder.h

    r8491c48 r3156582  
    3131
    3232/* AMD64 is little-endian */
    33 #define native_le2host(n)               n
     33#define native_le2host(n)               (n)
     34#define u64_le2host(n)          (n)
    3435
    3536#endif

  • arch/amd64/src/asm_utils.S

    r8491c48 r3156582  
    5959.global utext
    6060utext:
    61         xor %ax,%ax;
    62         mov %ax,%ds;
    63         mov %ax,%es;
    64         mov %ax,%fs;
    65         mov %ax,%gs;
    66610:
    6762        int $48
    … …  
    178173        push_all_gpr
    179174
    180         # trap_dispatcher(i, stack)
    181175        movq $(\i),%rdi   # %rdi - first parameter
    182176        movq %rbp, %rsi
    183177        addq $8, %rsi     # %rsi - second parameter - original stack
    184         call trap_dispatcher
     178        call trap_dispatcher    # trap_dispatcher(i, stack)
    185179
    186180# Test if this is interrupt with error word or not
    … …  
    217211h_start:
    218212        handler 0 IDT_ITEMS
    219 #       handler 64 128 
    220 #       handler 128 192
    221 #       handler 192 256
    222213h_end:
    223214       

  • arch/amd64/src/fpu_context.c

    r8491c48 r3156582  
    3232#include <cpu.h>
    3333
     34/** Save FPU (mmx, sse) context using fxsave instruction */
    3435void fpu_context_save(fpu_context_t *fctx)
    3536{
    … …  
    4445}
    4546
     47/** Restore FPU (mmx,sse) context using fxrstor instruction */
    4648void fpu_context_restore(fpu_context_t *fctx)
    4749{

  • arch/amd64/src/pm.c

    r8491c48 r3156582  
    9292          .granularity = 1,
    9393          .base_24_31  = 0 },
    94         /* KTEXT 32-bit protected */
     94        /* KTEXT 32-bit protected, for protected mode before long mode */
    9595        { .limit_0_15  = 0xffff,
    9696          .base_0_15   = 0,

  • arch/ia32/include/byteorder.h

    r8491c48 r3156582  
    3131
    3232/* IA-32 is little-endian */
    33 #define native_le2host(n)               n
     33#define native_le2host(n)               (n)
     34#define u64_le2host(n)          (n)
    3435
    3536#endif

  • arch/ia64/include/byteorder.h

    r8491c48 r3156582  
    3131
    3232/* IA-64 is little-endian */
    33 #define native_le2host(n)               n
     33#define native_le2host(n)               (n)
     34#define u64_le2host(n)          (n)
    3435
    3536#endif

  • arch/mips/Makefile.inc

    r8491c48 r3156582  
    11MIPS_TARGET=mipsel-linux-gnu
    2 
    32MIPS_CC_DIR=/usr/local/mipsel/bin
    43MIPS_BINUTILS_DIR=/usr/local/mipsel/bin
    … …  
    98OBJDUMP=$(MIPS_BINUTILS_DIR)/$(MIPS_TARGET)-objdump
    109OBJCOPY=$(MIPS_BINUTILS_DIR)/$(MIPS_TARGET)-objcopy
    11 BFD_NAME=elf32-tradlittlemips
    1210BFD_ARCH=mips
    1311
    … …  
    1513CFLAGS=$(DEFS) -mno-abicalls -G 0 -nostdlib -fno-builtin -O2  -fno-zero-initialized-in-bss
    1614LFLAGS=-M -N
     15BFD_ARCH=mips
    1716
    18 # It seems that on big endian either GCC or the simulators
    19 # have the swl/swr/lwl/lwr instructions wrong. Just for sure,
    20 # disable it with -mmemcpy (force calling memcpy instead of inlining)
     17# GCC 4.0.1 compiled for mipsEL has problems compiling in
     18# BigEndian mode with the swl/swr/lwl/lwr instructions.
     19# We have to compile it with mips-sgi-irix5 to get it right.
     20ifeq (${MACHINE},indy)
     21 MIPS_TARGET=mips-sgi-irix5
     22 MIPS_CC_DIR=/usr/local/mips/bin
     23 MIPS_BINUTILS_DIR=/usr/local/mips/bin
    2124
    22 ifeq (${MACHINE},indy)
    23  CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -march=r4600
     25 CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -march=r4600
    2426 BFD = ecoff-bigmips
    2527 KERNEL_LOAD_ADDRESS = 0x88002000
     28 BFD_NAME=elf32-big
    2629endif
    2730
    … …  
    3033 BFD = ecoff-littlemips
    3134 KERNEL_LOAD_ADDRESS = 0x80100000
     35 BFD_NAME=elf32-little
    3236endif
    3337
    3438ifeq (${MACHINE},bgxemul)
    35  CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -mips3
     39 MIPS_TARGET=mips-sgi-irix5
     40 MIPS_CC_DIR=/usr/local/mips/bin
     41 MIPS_BINUTILS_DIR=/usr/local/mips/bin
     42
     43 CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -mips3
    3644 BFD = ecoff-bigmips
    3745 KERNEL_LOAD_ADDRESS = 0x80100000
     46 BFD_NAME=elf32-big
    3847endif
    3948
    … …  
    4453 CFLAGS += -msoft-float -march=4kc
    4554 KERNEL_LOAD_ADDRESS = 0x80100000
     55 BFD_NAME=elf32-little
    4656endif
    4757
    … …  
    5262 CFLAGS += -msoft-float -mips3
    5363 KERNEL_LOAD_ADDRESS = 0x80100000
     64 BFD_NAME=elf32-little
    5465endif
    5566
    … …  
    7384        arch/mm/tlb.c \
    7485        arch/fpu_context.c \
    75         arch/fmath.c
     86        arch/fmath.c \
     87        arch/drivers/arc.c

  • arch/mips/_link.ld.in

    r8491c48 r3156582  
    3434                *(.sdata);
    3535                *(.reginfo);
     36                /* Unfortunately IRIX does not allow us
     37                 * to include this as a last section :-(
     38                 * BSS/SBSS addresses will be wrong */
     39                symbol_table = .;
     40                *(symtab.*);             
    3641        }
    3742        _gp = . + 0x8000;
    … …  
    4752        }
    4853
    49         mysymtab : {
    50                 symbol_table = .;
    51                 *(symtab.*);             /* Symbol table, must be LAST symbol!*/
    52         }
    5354        kdata_end = .;
    5455

  • arch/mips/include/byteorder.h

    r8491c48 r3156582  
    3232/* MIPS is little-endian */
    3333#ifdef BIG_ENDIAN
     34static inline __u64 u64_le2host(__u64 n)
     35{
     36        return ((n & 0xff) << 56) |
     37                ((n & 0xff00) << 40) |
     38                ((n & 0xff0000) << 24) |
     39                ((n & 0xff000000LL) << 8) |
     40                ((n & 0xff00000000LL) >>8) |
     41                ((n & 0xff0000000000LL) >> 24) |
     42                ((n & 0xff000000000000LL) >> 40) |
     43                ((n & 0xff00000000000000LL) >> 56);
     44}
     45
    3446static inline __native native_le2host(__native n)
    3547{
    … …  
    4052}
    4153#else
    42 #  define native_le2host(n)             n
     54#  define native_le2host(n)             (n)
     55#  define u64_le2host(n)                (n)
    4356#endif
    4457

  • arch/mips/include/console.h

    r8491c48 r3156582  
    3939void console_init(void);
    4040
    41 extern int bios_write(int fd, const char *buf, int size, int *cnt);
    42 
    43 
    4441#endif

  • arch/mips/include/interrupt.h

    r8491c48 r3156582  
    3030#define __INTERRUPT_H__
    3131
     32#include <arch/exception.h>
     33
    3234#define TIMER_INTERRUPT   7
    3335
    34 extern void interrupt(void);
     36extern void interrupt(struct exception_regdump *pstate);
    3537
    3638#endif

  • arch/mips/include/types.h

    r8491c48 r3156582  
    3333
    3434typedef signed char __s8;
     35typedef unsigned char __u8;
    3536
    36 typedef unsigned char __u8;
     37typedef signed short __s16;
    3738typedef unsigned short __u16;
     39
    3840typedef unsigned long __u32;
    39 typedef long long __u64;
     41typedef signed long __s32;
     42
     43typedef unsigned long long __u64;
     44typedef signed long long __s64;
    4045
    4146typedef __u32 __address;

  • arch/mips/src/asm.S

    r8491c48 r3156582  
    118118
    119119
    120 .global bios_write
    121 bios_write:
    122         lw      $2, 0x80001020
    123         lw      $2, 0x6c($2)
    124         j       $2
    125         nop
    126        
    127120.global cpu_halt
    128121cpu_halt:

  • arch/mips/src/console.c

    r8491c48 r3156582  
    3232#include <arch/console.h>
    3333#include <arch.h>
     34#include <arch/drivers/arc.h>
     35#include <arch/arch.h>
    3436
    35 static void arc_putchar(const char ch)
    36 {
    37         int cnt;
    38         pri_t pri;
    39 
    40         /* TODO: Should be spinlock? */
    41         pri = cpu_priority_high();
    42         bios_write(1, &ch, 1, &cnt);
    43         cpu_priority_restore(pri);
    44        
    45 }
    46 
     37/** Putchar that works with MSIM & gxemul */
    4738static void cons_putchar(const char ch)
    4839{
    … …  
    5041}
    5142
    52 
     43/** Putchar that works with simics */
    5344static void serial_putchar(const char ch)
    5445{
    … …  
    6859void console_init(void)
    6960{
     61        if (arc_enabled())
     62                putchar_func = arc_putchar;
    7063        /* The LSR on the start usually contains this value */
    71         if (*SERIAL_LSR == 0x60)
     64        else if (*SERIAL_LSR == 0x60)
    7265                putchar_func = serial_putchar;
    7366        else

  • arch/mips/src/exception.c

    r8491c48 r3156582  
    6666        switch (excno) {
    6767                case EXC_Int:
    68                         interrupt();
     68                        interrupt(pstate);
    6969                        break;
    7070                case EXC_TLBL:

  • arch/mips/src/interrupt.c

    r8491c48 r3156582  
    3333#include <time/clock.h>
    3434#include <panic.h>
     35#include <print.h>
     36#include <symtab.h>
     37#include <arch/drivers/arc.h>
     38
     39static void print_regdump(struct exception_regdump *pstate)
     40{
     41        char *pcsymbol = "";
     42        char *rasymbol = "";
     43
     44        char *s = get_symtab_entry(pstate->epc);
     45        if (s)
     46                pcsymbol = s;
     47        s = get_symtab_entry(pstate->ra);
     48        if (s)
     49                rasymbol = s;
     50       
     51        printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol,
     52               pstate->ra,rasymbol);
     53}
    3554
    3655pri_t cpu_priority_high(void)
    … …  
    5877}
    5978
    60 void interrupt(void)
     79void interrupt(struct exception_regdump *pstate)
    6180{
    6281        __u32 cause;
    … …  
    7089                        switch (i) {
    7190                                case 0: /* SW0 - Software interrupt 0 */
    72                                         cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */
     91                                        cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
    7392                                        break;
    7493                                case 1: /* SW1 - Software interrupt 1 */
    75                                         cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */
     94                                        cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
    7695                                        break;
    7796                                case 2: /* IRQ0 */
    … …  
    8099                                case 5: /* IRQ3 */
    81100                                case 6: /* IRQ4 */
     101                                        print_regdump(pstate);
    82102                                        panic("unhandled interrupt %d\n", i);
    83103                                        break;

  • arch/mips/src/mips.c

    r8491c48 r3156582  
    3737#include <memstr.h>
    3838#include <arch/interrupt.h>
     39#include <arch/drivers/arc.h>
    3940
    4041#include <print.h>
    … …  
    5354        /* It is not assumed by default */
    5455        cpu_priority_high();
     56
     57        init_arc();
    5558
    5659        /* Copy the exception vectors to the right places */
    … …  
    8083
    8184        console_init();
     85        arc_print_memory_map();
    8286}
    8387
    … …  
    111115        supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
    112116}
    113 
    114 

  • arch/mips/src/mm/tlb.c

    r8491c48 r3156582  
    4141        char *sym2 = "";
    4242
    43         if (THREAD) {
    44                 char *s = get_symtab_entry(pstate->epc);
    45                 if (s)
    46                         symbol = s;
    47                 s = get_symtab_entry(pstate->ra);
    48                 if (s)
    49                         sym2 = s;
    50         }
     43        char *s = get_symtab_entry(pstate->epc);
     44        if (s)
     45                symbol = s;
     46        s = get_symtab_entry(pstate->ra);
     47        if (s)
     48                sym2 = s;
    5149        panic("%X: tlb_refill exception at %X(%s<-%s)\n", cp0_badvaddr_read(),
    5250              pstate->epc, symbol,sym2);
    … …  
    5755        char *symbol = "";
    5856
    59         if (THREAD) {
    60                 char *s = get_symtab_entry(pstate->epc);
    61                 if (s)
    62                         symbol = s;
    63         }
     57        char *s = get_symtab_entry(pstate->epc);
     58        if (s)
     59                symbol = s;
    6460        panic("%X: TLB exception at %X(%s)\n", cp0_badvaddr_read(),
    6561              pstate->epc, symbol);

  • arch/ppc/include/byteorder.h

    r8491c48 r3156582  
    4141 *
    4242 */
     43static inline __u64 u64_le2host(__u64 n)
     44{
     45        return ((n & 0xff) << 56) |
     46                ((n & 0xff00) << 40) |
     47                ((n & 0xff0000) << 24) |
     48                ((n & 0xff000000LL) << 8) |
     49                ((n & 0xff00000000LL) >>8) |
     50                ((n & 0xff0000000000LL) >> 24) |
     51                ((n & 0xff000000000000LL) >> 40) |
     52                ((n & 0xff00000000000000LL) >> 56);
     53}
    4354static inline __native native_le2host(__native n)
    4455{

  • src/debug/symtab.c

    r8491c48 r3156582  
    4040
    4141        for (i=1;symbol_table[i].address_le;++i) {
    42                 if (addr < native_le2host(symbol_table[i].address_le))
     42                if (addr < u64_le2host(symbol_table[i].address_le))
    4343                        break;
    4444        }
    45         if (addr >= native_le2host(symbol_table[i-1].address_le))
     45        if (addr >= u64_le2host(symbol_table[i-1].address_le))
    4646                return symbol_table[i-1].symbol_name;
    4747        return NULL;

  • tools/genmap.py

    r8491c48 r3156582  
    99
    1010
    11 funcline = re.compile(r'([0-9a-f]+)\s+[lg]\s+F\s+\.text\s+([0-9a-f]+)\s+(.*)$')
     11funcline = re.compile(r'([0-9a-f]+)\s+[lg]\s+.\s+\.text\s+([0-9a-f]+)\s+(.*)$')
    1212bssline = re.compile(r'([0-9a-f]+)\s+[lg]\s+[a-zA-Z]\s+\.bss\s+([0-9a-f]+)\s+(.*)$')
    1313dataline = re.compile(r'([0-9a-f]+)\s+[lg]\s+[a-zA-Z]\s+\.data\s+([0-9a-f]+)\s+(.*)$')
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