Changes in uspace/drv/bus/pci/pciintel/pci.c [690d2e7:2df6f6fe] in mainline
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uspace/drv/bus/pci/pciintel/pci.c
r690d2e7 r2df6f6fe 38 38 39 39 #include <assert.h> 40 #include <byteorder.h>41 40 #include <stdio.h> 42 41 #include <errno.h> … … 232 231 void *addr = bus->conf_data_port + (reg & 3); 233 232 234 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));233 pio_write_32(bus->conf_addr_port, conf_addr); 235 234 236 235 switch (len) { 237 236 case 1: 238 /* No endianness change for 1 byte */239 237 buf[0] = pio_read_8(addr); 240 238 break; 241 239 case 2: 242 ((uint16_t *) buf)[0] = uint16_t_le2host(pio_read_16(addr));240 ((uint16_t *) buf)[0] = pio_read_16(addr); 243 241 break; 244 242 case 4: 245 ((uint32_t *) buf)[0] = uint32_t_le2host(pio_read_32(addr));243 ((uint32_t *) buf)[0] = pio_read_32(addr); 246 244 break; 247 245 } … … 256 254 fibril_mutex_lock(&bus->conf_mutex); 257 255 258 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg); 256 uint32_t conf_addr; 257 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg); 259 258 void *addr = bus->conf_data_port + (reg & 3); 260 259 261 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));260 pio_write_32(bus->conf_addr_port, conf_addr); 262 261 263 262 switch (len) { 264 263 case 1: 265 /* No endianness change for 1 byte */266 264 pio_write_8(addr, buf[0]); 267 265 break; 268 266 case 2: 269 pio_write_16(addr, host2uint16_t_le(((uint16_t *) buf)[0]));267 pio_write_16(addr, ((uint16_t *) buf)[0]); 270 268 break; 271 269 case 4: 272 pio_write_32(addr, host2uint32_t_le(((uint32_t *) buf)[0]));270 pio_write_32(addr, ((uint32_t *) buf)[0]); 273 271 break; 274 272 } … … 652 650 got_res = true; 653 651 654 655 assert(hw_resources.count > 1);656 assert(hw_resources.resources[0].type == IO_RANGE);657 assert(hw_resources.resources[0].res.io_range.size >= 4);658 659 assert(hw_resources.resources[1].type == IO_RANGE);660 assert(hw_resources.resources[1].res.io_range.size >= 4);661 662 652 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".", 663 653 hw_resources.resources[0].res.io_range.address); 664 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".", 665 hw_resources.resources[1].res.io_range.address); 654 655 assert(hw_resources.count > 0); 656 assert(hw_resources.resources[0].type == IO_RANGE); 657 assert(hw_resources.resources[0].res.io_range.size == 8); 666 658 667 659 bus->conf_io_addr = 668 660 (uint32_t) hw_resources.resources[0].res.io_range.address; 669 bus->conf_io_data = 670 (uint32_t) hw_resources.resources[1].res.io_range.address; 671 672 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4, 661 662 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8, 673 663 &bus->conf_addr_port)) { 674 664 ddf_msg(LVL_ERROR, "Failed to enable configuration ports."); … … 676 666 goto fail; 677 667 } 678 if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4, 679 &bus->conf_data_port)) { 680 ddf_msg(LVL_ERROR, "Failed to enable configuration ports."); 681 rc = EADDRNOTAVAIL; 682 goto fail; 683 } 668 bus->conf_data_port = (char *) bus->conf_addr_port + 4; 684 669 685 670 /* Make the bus device more visible. It has no use yet. */
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