Changes in / [ff586e06:2d0c3a6] in mainline


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Files:
3 added
8 edited

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Removed

  • boot/arch/arm32/Makefile.inc

    rff586e06 r2d0c3a6  
    4242
    4343RD_SRVS_ESSENTIAL += \
     44        $(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24ts \
    4445        $(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
    4546

  • kernel/arch/arm32/src/mach/gta02/gta02.c

    rff586e06 r2d0c3a6  
    221221                }
    222222        }
     223
     224        /* Enable interrupts from ADC */
     225        s3c24xx_irqc_src_enable(&gta02_irqc, S3C24XX_INT_ADC);
     226
     227        /* Enable interrupts from ADC sub-sources */
     228        s3c24xx_irqc_subsrc_enable(&gta02_irqc, S3C24XX_SUBINT_ADC_S);
     229        s3c24xx_irqc_subsrc_enable(&gta02_irqc, S3C24XX_SUBINT_TC);
    223230}
    224231

  • kernel/genarch/include/drivers/s3c24xx_uart/s3c24xx_uart.h

    rff586e06 r2d0c3a6  
    6060} s3c24xx_uart_io_t;
    6161
     62/* Bits in UTRSTAT register */
     63#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
     64#define S3C24XX_UTRSTAT_RDATA           0x1
     65
     66/* Bits in UFSTAT register */
     67#define S3C24XX_UFSTAT_TX_FULL          0x4000
     68#define S3C24XX_UFSTAT_RX_FULL          0x0040
     69#define S3C24XX_UFSTAT_RX_COUNT         0x002f
     70
     71/* Bits in UCON register */
     72#define UCON_RX_INT_LEVEL               0x100
     73
     74/* Bits in UFCON register */
     75#define UFCON_TX_FIFO_TLEVEL_EMPTY      0x00
     76#define UFCON_RX_FIFO_TLEVEL_1B         0x00
     77#define UFCON_FIFO_ENABLE               0x01
     78
     79
    6280/** S3C24xx UART instance */
    6381typedef struct {

  • kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c

    rff586e06 r2d0c3a6  
    4646#include <sysinfo/sysinfo.h>
    4747#include <str.h>
    48 
    49 /* Bits in UTRSTAT register */
    50 #define S3C24XX_UTRSTAT_TX_EMPTY        0x4
    51 #define S3C24XX_UTRSTAT_RDATA           0x1
    52 
    53 #define S3C24XX_UFSTAT_TX_FULL          0x4000
    54 #define S3C24XX_UFSTAT_RX_FULL          0x0040
    55 #define S3C24XX_UFSTAT_RX_COUNT         0x002f
    5648
    5749static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
    … …  
    129121
    130122        /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
    131         pio_write_32(&uart->io->ufcon, 0x01);
     123        pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
     124            UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
    132125
    133126        /* Set RX interrupt to pulse mode */
    134127        pio_write_32(&uart->io->ucon,
    135             pio_read_32(&uart->io->ucon) & ~(1 << 8));
     128            pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
    136129
    137130        if (!fb_exported) {

  • uspace/Makefile

    rff586e06 r2d0c3a6  
    6666        srv/hid/adb_mouse \
    6767        srv/hid/char_mouse \
     68        srv/hid/s3c24xx_ts \
    6869        srv/hid/fb \
    6970        srv/hid/kbd \

  • uspace/app/init/init.c

    rff586e06 r2d0c3a6  
    277277        srv_start("/srv/adb_ms");
    278278        srv_start("/srv/char_ms");
     279        srv_start("/srv/s3c24ts");
    279280       
    280281        spawn("/srv/fb");

  • uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c

    rff586e06 r2d0c3a6  
    5353#define NAME "s3c24ser"
    5454#define NAMESPACE "char"
    55 
    56 /* Bits in UTRSTAT register */
    57 #define S3C24XX_UTRSTAT_TX_EMPTY        0x4
    58 #define S3C24XX_UTRSTAT_RDATA           0x1
    59 
    60 /* Bits in UFSTAT register */
    61 #define S3C24XX_UFSTAT_TX_FULL          0x4000
    62 #define S3C24XX_UFSTAT_RX_FULL          0x0040
    63 #define S3C24XX_UFSTAT_RX_COUNT         0x002f
    6455
    6556static irq_cmd_t uart_irq_cmds[] = {
    … …  
    169160                }
    170161
    171                 if (status & 0x0f)
     162                if (status != 0)
    172163                        printf(NAME ": Error status 0x%x\n", status);
    173164        }
    … …  
    202193
    203194        /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
    204         pio_write_32(&uart->io->ufcon, 0x01);
     195        pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
     196            UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
    205197
    206198        /* Set RX interrupt to pulse mode */
    207199        pio_write_32(&uart->io->ucon,
    208             pio_read_32(&uart->io->ucon) & ~(1 << 8));
     200            pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
    209201
    210202        return EOK;

  • uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.h

    rff586e06 r2d0c3a6  
    5858} s3c24xx_uart_io_t;
    5959
     60/* Bits in UTRSTAT register */
     61#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
     62#define S3C24XX_UTRSTAT_RDATA           0x1
     63
     64/* Bits in UFSTAT register */
     65#define S3C24XX_UFSTAT_TX_FULL          0x4000
     66#define S3C24XX_UFSTAT_RX_FULL          0x0040
     67#define S3C24XX_UFSTAT_RX_COUNT         0x002f
     68
     69/* Bits in UCON register */
     70#define UCON_RX_INT_LEVEL               0x100
     71
     72/* Bits in UFCON register */
     73#define UFCON_TX_FIFO_TLEVEL_EMPTY      0x00
     74#define UFCON_RX_FIFO_TLEVEL_1B         0x00
     75#define UFCON_FIFO_ENABLE               0x01
     76
     77
    6078/** S3C24xx UART instance */
    6179typedef struct {
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