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Changeset 0747468 in mainline


Ignore:
Timestamp:
2012-07-14T09:27:31Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial
Children:
97c7682
Parents:
ee685630
Message:

arm32: Move common definitions to common header.

Restrict including of arch specific headers.

Location:
kernel/arch/arm32/include/mm
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/mm/page.h

    ree685630 r0747468  
    3737#define KERN_arm32_PAGE_H_
    3838
     39#include <arch/mm/frame.h>
     40#include <mm/mm.h>
     41#include <arch/exception.h>
     42#include <trace.h>
     43
     44#define PAGE_WIDTH      FRAME_WIDTH
     45#define PAGE_SIZE       FRAME_SIZE
     46
    3947#ifdef MACHINE_beagleboardxm
    4048#ifndef __ASM__
     
    5563#endif
    5664
     65/* Number of entries in each level. */
     66#define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
     67#define PTL1_ENTRIES_ARCH       0
     68#define PTL2_ENTRIES_ARCH       0
     69/* coarse page tables used (256 * 4 = 1KB per page) */
     70#define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
     71
     72/* Page table sizes for each level. */
     73#define PTL0_SIZE_ARCH          FOUR_FRAMES
     74#define PTL1_SIZE_ARCH          0
     75#define PTL2_SIZE_ARCH          0
     76#define PTL3_SIZE_ARCH          ONE_FRAME
     77
     78/* Macros calculating indices into page tables for each level. */
     79#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
     80#define PTL1_INDEX_ARCH(vaddr)  0
     81#define PTL2_INDEX_ARCH(vaddr)  0
     82#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
     83
     84/* Get PTE address accessors for each level. */
     85#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
     86        ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
     87#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
     88        (ptl1)
     89#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
     90        (ptl2)
     91#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
     92        ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
     93
     94/* Set PTE address accessors for each level. */
     95#define SET_PTL0_ADDRESS_ARCH(ptl0) \
     96        (set_ptl0_addr((pte_t *) (ptl0)))
     97#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
     98        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
     99#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
     100#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
     101#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
     102        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
     103
     104/* Get PTE flags accessors for each level. */
     105#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
     106        get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
     107#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
     108        PAGE_PRESENT
     109#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
     110        PAGE_PRESENT
     111#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
     112        get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
     113
     114/* Set PTE flags accessors for each level. */
     115#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
     116        set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
     117#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
     118#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
     119#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
     120        set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
     121
    57122#if defined(PROCESSOR_armv7_a)
    58123#include "page_armv7.h"
  • kernel/arch/arm32/include/mm/page_armv4.h

    ree685630 r0747468  
    3838#define KERN_arm32_PAGE_armv4_H_
    3939
    40 #include <arch/mm/frame.h>
    41 #include <mm/mm.h>
    42 #include <arch/exception.h>
    43 #include <trace.h>
    44 
    45 #define PAGE_WIDTH      FRAME_WIDTH
    46 #define PAGE_SIZE       FRAME_SIZE
    47 
    48 /* Number of entries in each level. */
    49 #define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
    50 #define PTL1_ENTRIES_ARCH       0
    51 #define PTL2_ENTRIES_ARCH       0
    52 /* coarse page tables used (256 * 4 = 1KB per page) */
    53 #define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
    54 
    55 /* Page table sizes for each level. */
    56 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    57 #define PTL1_SIZE_ARCH          0
    58 #define PTL2_SIZE_ARCH          0
    59 #define PTL3_SIZE_ARCH          ONE_FRAME
    60 
    61 /* Macros calculating indices into page tables for each level. */
    62 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
    63 #define PTL1_INDEX_ARCH(vaddr)  0
    64 #define PTL2_INDEX_ARCH(vaddr)  0
    65 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
    66 
    67 /* Get PTE address accessors for each level. */
    68 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    69         ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    70 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    71         (ptl1)
    72 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
    73         (ptl2)
    74 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    75         ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    76 
    77 /* Set PTE address accessors for each level. */
    78 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
    79         (set_ptl0_addr((pte_t *) (ptl0)))
    80 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    81         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    82 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    83 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    84 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    85         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    86 
    87 /* Get PTE flags accessors for each level. */
    88 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    89         get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    90 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    91         PAGE_PRESENT
    92 #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
    93         PAGE_PRESENT
    94 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    95         get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    96 
    97 /* Set PTE flags accessors for each level. */
    98 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    99         set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    100 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    101 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    102 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    103         set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
     40#ifndef KERN_arm32_PAGE_H_
     41#error "Do not include arch specific page.h directly use generic page.h instead"
     42#endif
    10443
    10544/* Macros for querying the last-level PTE entries. */
  • kernel/arch/arm32/include/mm/page_armv7.h

    ree685630 r0747468  
    3737#define KERN_arm32_PAGE_armv7_H_
    3838
    39 #include <arch/mm/frame.h>
    40 #include <mm/mm.h>
    41 #include <arch/exception.h>
    42 #include <trace.h>
    43 
    44 #define PAGE_WIDTH      FRAME_WIDTH
    45 #define PAGE_SIZE       FRAME_SIZE
    46 
    47 /* Number of entries in each level. */
    48 #define PTL0_ENTRIES_ARCH       (1 << 12)       /* 4096 */
    49 #define PTL1_ENTRIES_ARCH       0
    50 #define PTL2_ENTRIES_ARCH       0
    51 /* coarse page tables used (256 * 4 = 1KB per page) */
    52 #define PTL3_ENTRIES_ARCH       (1 << 8)        /* 256 */
    53 
    54 /* Page table sizes for each level. */
    55 #define PTL0_SIZE_ARCH          FOUR_FRAMES
    56 #define PTL1_SIZE_ARCH          0
    57 #define PTL2_SIZE_ARCH          0
    58 #define PTL3_SIZE_ARCH          ONE_FRAME
    59 
    60 /* Macros calculating indices into page tables for each level. */
    61 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
    62 #define PTL1_INDEX_ARCH(vaddr)  0
    63 #define PTL2_INDEX_ARCH(vaddr)  0
    64 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
    65 
    66 /* Get PTE address accessors for each level. */
    67 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    68         ((pte_t *) ((((pte_t *)(ptl0))[(i)].l0).coarse_table_addr << 10))
    69 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    70         (ptl1)
    71 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
    72         (ptl2)
    73 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    74         ((uintptr_t) ((((pte_t *)(ptl3))[(i)].l1).frame_base_addr << 12))
    75 
    76 /* Set PTE address accessors for each level. */
    77 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
    78         (set_ptl0_addr((pte_t *) (ptl0)))
    79 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    80         (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
    81 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
    82 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
    83 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    84         (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
    85 
    86 /* Get PTE flags accessors for each level. */
    87 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    88         get_pt_level0_flags((pte_t *) (ptl0), (size_t) (i))
    89 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    90         PAGE_PRESENT
    91 #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
    92         PAGE_PRESENT
    93 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    94         get_pt_level1_flags((pte_t *) (ptl3), (size_t) (i))
    95 
    96 /* Set PTE flags accessors for each level. */
    97 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    98         set_pt_level0_flags((pte_t *) (ptl0), (size_t) (i), (x))
    99 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
    100 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
    101 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    102         set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
     39#ifndef KERN_arm32_PAGE_H_
     40#error "Do not include arch specific page.h directly use generic page.h instead"
     41#endif
    10342
    10443/* Macros for querying the last-level PTE entries. */
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