Changes between Version 17 and Version 18 of VASFeatures
- Timestamp:
- 2012-01-25T23:40:25Z (13 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
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VASFeatures
v17 v18 9 9 48-bit virtual address width 10 10 11 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||12 || `FFFF800000000000` || 128 TiB || none || kernel identity^[#amd64f2 (2)]^ ||13 || `0000800000000000` || 16776960 TiB || VA hole^[#amd64f1 (1)]^ || ||14 || `0000000000000000` || 128 TiB || none || uspace non-identity ||11 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 12 || `FFFF800000000000` || 128 TiB || none || 13 || `0000800000000000` || 16776960 TiB || VA hole^[#amd64f1 (1)]^ || 14 || `0000000000000000` || 128 TiB || none || 15 15 16 16 17 17 1. [=#amd64f1] depends on implementation, but in practice current implementations use 48 bits 18 2. [=#amd64f2] physical addresses beyond the limit of physical memory are mapped non-identity19 18 20 19 ---- … … 22 21 == arm32 == 23 22 24 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||25 || `80000000` || 2 GiB || high vectors at fixed VA^[#arm32f1 (1)] || kernel identity^[#arm32f2 (2)]^ ||26 || `00000000` || 2 GiB || low vectors at fixed VA^[#arm32f 3 (3)] || uspace non-identity||23 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 24 || `80000000` || 2 GiB || high vectors at fixed VA^[#arm32f1 (1)] || 25 || `00000000` || 2 GiB || low vectors at fixed VA^[#arm32f2 (2)] || 27 26 28 27 29 28 1. [=#arm32f1] `0xFFFF0000` - `0xFFFF001C` 30 1. [=#arm32f1] physical addresses beyond the limit of physical memory are mapped non-identity 31 1. [=#arm32f3] `0x00000000` - `0x0000001C` 29 1. [=#arm32f2] `0x00000000` - `0x0000001C` 32 30 33 31 ---- … … 35 33 == ia32 == 36 34 37 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| 38 || `80000000` || 2 GiB || none || kernel identity^[#ia32f1 (1)]^ || 39 || `00000000` || 2 GiB || none || uspace non-identity || 40 41 1. [=#ia32f1] physical addresses beyond the limit of physical memory are mapped non-identity 35 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 36 || `80000000` || 2 GiB || none || 37 || `00000000` || 2 GiB || none || 42 38 43 39 ---- … … 49 45 (3 + 51)-bit virtual address width 50 46 51 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||52 || `FFFC000000000000` || 1 PiB || VRN 7, high || kernel identity ||53 || `E004000000000000` || 2046 PiB || VA hole || ||54 || `E000000000000000` || 1 PiB || VRN 7, low || kernel identity ||55 || `DFFC000000000000` || 1 PiB || VRN 6, high || uspace non-identity ||56 || `C004000000000000` || 2046 PiB || VA hole || ||57 || `C000000000000000` || 1 PiB || VRN 6, low || uspace non-identity ||58 || `BFFC000000000000` || 1 PiB || VRN 5, high || uspace non-identity ||59 || `A004000000000000` || 2046 PiB || VA hole || ||60 || `A000000000000000` || 1 PiB || VRN 5, low || uspace non-identity ||61 || `9FFC000000000000` || 1 PiB || VRN 4, high || uspace non-identity ||62 || `8004000000000000` || 2046 PiB || VA hole || ||63 || `8000000000000000` || 1 PiB || VRN 4, low || uspace non-identity ||64 || `7FFC000000000000` || 1 PiB || VRN 3, high || uspace non-identity ||65 || `6004000000000000` || 2046 PiB || VA hole || ||66 || `6000000000000000` || 1 PiB || VRN 3, low || uspace non-identity ||67 || `5FFC000000000000` || 1 PiB || VRN 2, high || uspace non-identity ||68 || `4004000000000000` || 2046 PiB || VA hole || ||69 || `4000000000000000` || 1 PiB || VRN 2, low || uspace non-identity ||70 || `3FFC000000000000` || 1 PiB || VRN 1, high || uspace non-identity ||71 || `2004000000000000` || 2046 PiB || VA hole || ||72 || `2000000000000000` || 1 PiB || VRN 1, low || uspace non-identity ||73 || `1FFC000000000000` || 1 PiB || VRN 0, high || uspace non-identity ||74 || `0004000000000000` || 2046 PiB || VA hole || ||75 || `0000000000000000` || 1 PiB || VRN 0, low || uspace non-identity ||47 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 48 || `FFFC000000000000` || 1 PiB || VRN 7, high || 49 || `E004000000000000` || 2046 PiB || VA hole || 50 || `E000000000000000` || 1 PiB || VRN 7, low || 51 || `DFFC000000000000` || 1 PiB || VRN 6, high || 52 || `C004000000000000` || 2046 PiB || VA hole || 53 || `C000000000000000` || 1 PiB || VRN 6, low || 54 || `BFFC000000000000` || 1 PiB || VRN 5, high || 55 || `A004000000000000` || 2046 PiB || VA hole || 56 || `A000000000000000` || 1 PiB || VRN 5, low || 57 || `9FFC000000000000` || 1 PiB || VRN 4, high || 58 || `8004000000000000` || 2046 PiB || VA hole || 59 || `8000000000000000` || 1 PiB || VRN 4, low || 60 || `7FFC000000000000` || 1 PiB || VRN 3, high || 61 || `6004000000000000` || 2046 PiB || VA hole || 62 || `6000000000000000` || 1 PiB || VRN 3, low || 63 || `5FFC000000000000` || 1 PiB || VRN 2, high || 64 || `4004000000000000` || 2046 PiB || VA hole || 65 || `4000000000000000` || 1 PiB || VRN 2, low || 66 || `3FFC000000000000` || 1 PiB || VRN 1, high || 67 || `2004000000000000` || 2046 PiB || VA hole || 68 || `2000000000000000` || 1 PiB || VRN 1, low || 69 || `1FFC000000000000` || 1 PiB || VRN 0, high || 70 || `0004000000000000` || 2046 PiB || VA hole || 71 || `0000000000000000` || 1 PiB || VRN 0, low || 76 72 77 73 === Itanium 2 === 78 74 79 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||80 || `E000000000000000` || 2 EiB || VRN 7 || kernel identity ||81 || `C000000000000000` || 2 EiB || VRN 6 || uspace non-identity ||82 || `A000000000000000` || 2 EiB || VRN 5 || uspace non-identity ||83 || `8000000000000000` || 2 EiB || VRN 4 || uspace non-identity ||84 || `6000000000000000` || 2 EiB || VRN 3 || uspace non-identity ||85 || `4000000000000000` || 2 EiB || VRN 2 || uspace non-identity ||86 || `2000000000000000` || 2 EiB || VRN 1 || uspace non-identity ||87 || `0000000000000000` || 2 EiB || VRN 0 || uspace non-identity ||75 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 76 || `E000000000000000` || 2 EiB || VRN 7 || 77 || `C000000000000000` || 2 EiB || VRN 6 || 78 || `A000000000000000` || 2 EiB || VRN 5 || 79 || `8000000000000000` || 2 EiB || VRN 4 || 80 || `6000000000000000` || 2 EiB || VRN 3 || 81 || `4000000000000000` || 2 EiB || VRN 2 || 82 || `2000000000000000` || 2 EiB || VRN 1 || 83 || `0000000000000000` || 2 EiB || VRN 0 || 88 84 89 85 ---- … … 91 87 == mips32 == 92 88 93 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||94 || `E0000000` || 512 MiB || kseg3, kernel || unused ||95 || `C0000000` || 512 MiB || ksseg, kernel || unused ||96 || `A0000000` || 512 MiB || kseg1, kernel uncached^[#mips32f1 (1)]^ || `hw_map()` ||97 || `80000000` || 512 MiB || kseg0, kernel identity^[#mips32f2 (2)]^ || kernel identity ||98 || `00000000` || 2 GiB || kuseg, uspace || uspace non-identity ||89 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 90 || `E0000000` || 512 MiB || kseg3, kernel || 91 || `C0000000` || 512 MiB || ksseg, kernel || 92 || `A0000000` || 512 MiB || kseg1, kernel uncached^[#mips32f1 (1)]^ || 93 || `80000000` || 512 MiB || kseg0, kernel identity^[#mips32f2 (2)]^ || 94 || `00000000` || 2 GiB || kuseg, uspace || 99 95 100 96 1. [=#mips32f1] maps to physical 0, uncached, bypasses TLB … … 106 102 == ppc32 == 107 103 108 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| 109 || `80000000` || 2 GiB || none || kernel identity^[#ppc32f1 (1)]^ || 110 || `00000000` || 2 GiB || none || uspace non-identity || 111 112 1. [=#ppc32f1] physical addresses beyond the limit of physical memory are mapped non-identity 104 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 105 || `80000000` || 2 GiB || none || 106 || `00000000` || 2 GiB || none || 113 107 114 108 ---- … … 120 114 44-bit virtual address width 121 115 122 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||123 || `FFFFF80000000000` || 8 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ ||124 || `0000080000000000` || 16777200 TiB || VA hole^[#sparc64f2 (2)]^ || ||125 || `0000000000000000` || 8 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ ||116 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 117 || `FFFFF80000000000` || 8 TiB || kernel^[#sparc64f1 (1)]^ || 118 || `0000080000000000` || 16777200 TiB || VA hole^[#sparc64f2 (2)]^ || 119 || `0000000000000000` || 8 TiB || kernel^[#sparc64f1 (1)]^ || 126 120 127 121 … … 130 124 64-bit virtual address width 131 125 132 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||133 || `0000000000000000` || 16 EiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ ||126 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 127 || `0000000000000000` || 16 EiB || kernel^[#sparc64f1 (1)]^ || 134 128 135 129 … … 138 132 48-bit virtual address width 139 133 140 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| = '''HelenOS use''' =||141 || `FFFF800000000000` || 128 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ ||142 || `0000800000000000` || 16776960 TiB || VA hole^[#sparc64f 4 (4)], [#sparc64f5 (5)]^ ||||143 || `0000000000000000` || 128 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ ||134 ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =|| 135 || `FFFF800000000000` || 128 TiB || kernel^[#sparc64f1 (1)]^ || 136 || `0000800000000000` || 16776960 TiB || VA hole^[#sparc64f3 (3)], [#sparc64f4 (4)]^ || 137 || `0000000000000000` || 128 TiB || kernel^[#sparc64f1 (1)]^ || 144 138 145 139 1. [=#sparc64f1] both kernel and uspace run in separated 64-bit address spaces 146 140 2. [=#sparc64f2] no code within 4GiB reach of the VA hole on UltraSPARC I and II 147 3. [=#sparc64f3] physical addresses beyond the limit of physical memory are identity mapped, uncachable 148 4. [=#sparc64f4] no code within 4GiB reach of the VA hole on T1 149 5. [=#sparc64f5] no code within 8KiB below VA hole on T2 141 3. [=#sparc64f3] no code within 4GiB reach of the VA hole on T1 142 4. [=#sparc64f4] no code within 8KiB below VA hole on T2
