11 | | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
12 | | || `FFFF800000000000` || 128 TiB || none || kernel identity^(2)^ || |
13 | | || `0000800000000000` || 16776960 TiB || VA hole^(1)^ || || |
14 | | || `0000000000000000` || 128 TiB || none || uspace non-identity || |
| 11 | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
| 12 | || `FFFF800000000000` || 128 TiB || none || kernel identity^[#amd64f2 (2)]^ || |
| 13 | || `0000800000000000` || 16776960 TiB || VA hole^[#amd64f1 (1)]^ || || |
| 14 | || `0000000000000000` || 128 TiB || none || uspace non-identity || |
| 50 | |
| 51 | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
| 52 | || `E0000000` || 512 MiB || kseg3, kernel || unused || |
| 53 | || `C0000000` || 512 MiB || ksseg, kernel || unused || |
| 54 | || `A0000000` || 512 MiB || kseg1, kernel uncached^[#mips32f1 (1)]^ || `hw_map()` || |
| 55 | || `80000000` || 512 MiB || kseg0, kernel identity^[#mips32f2 (2)]^ || kernel identity || |
| 56 | || `00000000` || 2 GiB || kuseg, uspace || uspace non-identity || |
52 | | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
53 | | || `E0000000` || 512 MiB || kseg3, kernel || unused || |
54 | | || `C0000000` || 512 MiB || ksseg, kernel || unused || |
55 | | || `A0000000` || 512 MiB || kseg1, kernel uncached^(1)^ || `hw_map()` || |
56 | | || `80000000` || 512 MiB || kseg0, kernel identity^(2)^ || kernel identity || |
57 | | || `00000000` || 2 GiB || kuseg, uspace || uspace non-identity || |
58 | | |
59 | | 1. maps to physical 0, uncached, bypasses TLB |
60 | | 2. maps to physical 0, cacheable, bypasses TLB |
| 58 | 1. [=#mips32f1] maps to physical 0, uncached, bypasses TLB |
| 59 | 2. [=#mips32f2] maps to physical 0, cacheable, bypasses TLB |
81 | | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
82 | | || `FFFFF80000000000` || 8 TiB || kernel^(1)^ || kernel identity^(3)^ || |
83 | | || `0000080000000000` || 16777200 TiB || VA hole^(2)^ || || |
84 | | || `0000000000000000` || 8 TiB || kernel^(1)^ || kernel identity^(3)^ || |
| 80 | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
| 81 | || `FFFFF80000000000` || 8 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ || |
| 82 | || `0000080000000000` || 16777200 TiB || VA hole^[#sparc64f2 (2)]^ || || |
| 83 | || `0000000000000000` || 8 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ || |
99 | | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
100 | | || `FFFF800000000000` || 128 TiB || kernel^(1)^ || kernel identity^(3)^ || |
101 | | || `0000800000000000` || 16776960 TiB || VA hole^(4), (5)^ || || |
102 | | || `0000000000000000` || 128 TiB || kernel^(1)^ || kernel identity^(3)^ || |
| 98 | ||= '''Starting address''' =||= '''Size''' =||= '''HW limitation''' =||= '''HelenOS use''' =|| |
| 99 | || `FFFF800000000000` || 128 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ || |
| 100 | || `0000800000000000` || 16776960 TiB || VA hole^[#sparc64f4 (4)], [#sparc64f5 (5)]^ || || |
| 101 | || `0000000000000000` || 128 TiB || kernel^[#sparc64f1 (1)]^ || kernel identity^[#sparc64f3 (3)]^ || |
104 | | 1. both kernel and uspace run in separated 64-bit address spaces |
105 | | 2. no code within 4GiB reach of the VA hole on UltraSPARC I and II |
106 | | 3. physical addresses beyond the limit of physical memory are identity mapped, uncachable |
107 | | 4. no code within 4GiB reach of the VA hole on T1 |
108 | | 5. no code within 8KiB below VA hole on T2 |
| 103 | 1. [=#sparc64f1] both kernel and uspace run in separated 64-bit address spaces |
| 104 | 2. [=#sparc64f2] no code within 4GiB reach of the VA hole on UltraSPARC I and II |
| 105 | 3. [=#sparc64f3] physical addresses beyond the limit of physical memory are identity mapped, uncachable |
| 106 | 4. [=#sparc64f4] no code within 4GiB reach of the VA hole on T1 |
| 107 | 5. [=#sparc64f5] no code within 8KiB below VA hole on T2 |