id	summary	reporter	owner	description	type	status	priority	milestone	component	version	resolution	keywords	cc	field_blocks	field_dependson	field_seealso
637	Do not set bits 13:0 in CP15 register 2 on ARM920T	Jakub Jermář	Jiri Svoboda	"ARM920T defines bits 13:0 of CP15 register 2 (translation table base) as reserved, yet the boot initialization code in boot/arch/arm32/src/mm.c and the page table management code in kernel/arch/arm32/include/arch/mm/page.h set them as if a newer version of the architecture was guaranteed:

{{{
static void init_boot_pt(void)
{
...
	uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
	val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
	TTBR0_write(val);
}

}}}

{{{
NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
{
        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
        TTBR0_write(val);
}
}}}"	defect	closed	major	0.7.0	helenos/kernel/arm32	mainline	fixed	ARM920T, ARMv4, gta02