id	summary	reporter	owner	description	type	status	priority	milestone	component	version	resolution	keywords	cc	field_blocks	field_dependson	field_seealso
636	Do not use DCCMVAU (c11, 1) on ARM920T	Jakub Jermář	Jiri Svoboda	"ARM920T does not implement the DCCMVAU / Clean ID cache entry operation, yet smc_coherence() and pt_coherence_m() use it:

{{{
CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
}}}

{{{
 #define smc_coherence(a) \
 do { \
        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
        write_barrier();               /* Wait for completion */\
        ICIALLU_write(0);              /* Flush ICache */\
        inst_barrier();                /* Wait for Inst refetch */\
}}}

{{{
#define pt_coherence_m(pt, count) \
 do { \
        for (unsigned i = 0; i < count; ++i) \
                DCCMVAU_write((uintptr_t)(pt + i)); \
        read_barrier(); \
 } while (0)
}}}
"	defect	closed	major	0.7.0	helenos/kernel/arm32	mainline	fixed	ARM920T, ARMv4, gta02