source: mainline/arch/amd64/src/cpu

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(edit) @1084a784   20 years jakub mips32 memory management work. TLB Refill Exception implemented … lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @b49f4ae   20 years ondrap Added architecture independent hooks for fpu lazy context switching. … lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @3396f59   20 years ondrap Fixed gdtr naming issues after ia32 changes. Fixed stack alignment on … lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(edit) @e515167d   20 years ondrap Added basic FPU context (not working). Added CPU utilities from ia32 … lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
(add) @89344d85   20 years ondrap Changes, that were needed to make it work on Bochs. - We CAN use the … lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
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