Changeset ffc277e in mainline for arch/mips/include


Ignore:
Timestamp:
2005-09-10T00:52:13Z (20 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f3a6c8e5
Parents:
b02e5d1
Message:

Cleanup of makefiles to have common options in one main makefile.

Add simple build process for different simulators for MIPS.
Added FPU context & lazy FPU context switching to MIPS.
Cleanup of MIPS linker script.
Moved MIPS kernel above 1MB. Not tested on real machine yet, but it might help.

There is something broken with gcc inlined memcpy (either simulator or gcc), it is disabled on BigEndian mips now.

Location:
arch/mips/include
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • arch/mips/include/asm.h

    rb02e5d1 rffc277e  
    3434#include <config.h>
    3535
    36 #define cpu_sleep()     ;
     36
     37static inline void cpu_sleep(void)
     38{
     39        /* Most of the simulators do not support */
     40/*      __asm__ volatile ("wait"); */
     41}
    3742
    3843/** Return base address of current stack

  • arch/mips/include/asm/boot.h

    rb02e5d1 rffc277e  
    3535
    3636/* Kernel startup address */
    37 #define KERNEL_STARTUP_ADDRESS 0x80000300
     37#define KERNEL_LOAD_ADDRESS 0x80100000
    3838
    3939

  • arch/mips/include/byteorder.h

    rb02e5d1 rffc277e  
    3131
    3232/* MIPS is little-endian */
    33 #define native_le2host(n)               n
     33#ifdef BIG_ENDIAN
     34static inline __native native_le2host(__native n)
     35{
     36        return ((n & 0xff) << 24) |
     37                ((n & 0xff00) << 8) |
     38                ((n & 0xff0000) >> 8) |
     39                ((n & 0xff000000) >> 24);
     40}
     41#else
     42#  define native_le2host(n)             n
     43#endif
    3444
    3545#endif

  • arch/mips/include/cp0.h

    rb02e5d1 rffc277e  
    3535#define cp0_status_exl_exception_bit    (1<<1)
    3636#define cp0_status_erl_error_bit        (1<<2)
     37#define cp0_status_um_bit               (1<<4)
    3738#define cp0_status_bev_bootstrap_bit    (1<<22)
    38 #define cp0_status_um_bit               (1<<4)
     39#define cp0_status_fpu_bit              (1<<29)
    3940
    4041#define cp0_status_im7_shift            15
    … …  
    4445 */
    4546#define cp0_compare_value               10000
     47
     48static inline void tlbp(void)
     49{
     50        __asm__ volatile ("tlbp");
     51}
     52
     53static inline void tlbr(void)
     54{
     55        __asm__ volatile ("tlbr");
     56}
     57static inline void tlbwi(void)
     58{
     59        __asm__ volatile ("tlbwi");
     60}
     61static inline void tlbwr(void)
     62{
     63        __asm__ volatile ("tlbwr");
     64}
     65
     66
    4667
    4768extern  __u32 cp0_index_read(void);
    … …  
    87108extern __u32 cp0_prid_read(void);
    88109
    89 extern void tlbp(void);
    90 extern void tlbr(void);
    91 extern void tlbwi(void);
    92 extern void tlbwr(void);
    93 
    94110#endif

  • arch/mips/include/exception.h

    rb02e5d1 rffc277e  
    9292
    9393extern void exception(struct exception_regdump *pstate);
    94 
     94extern void tlb_refill_entry(void);
     95extern void exception_entry(void);
     96extern void cache_error_entry(void);
    9597#endif

  • arch/mips/include/fpu_context.h

    rb02e5d1 rffc277e  
    3333
    3434struct fpu_context {
    35 /* TODO: define MIPS FPU context */
     35        __native dregs[32];
     36        __native cregs[32];
    3637};
    3738
    38 
    39 
    40 
    4139#endif

  • arch/mips/include/thread.h

    rb02e5d1 rffc277e  
    3030#define __mips_THREAD_H__
    3131
    32 #define ARCH_THREAD_DATA
     32#include <arch/exception.h>
     33
     34#define ARCH_THREAD_DATA   struct exception_regdump *pstate
    3335
    3436#endif
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