Changeset ff381a7 in mainline for boot

Timestamp:

2015-11-02T20:54:19Z (10 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d8513177

Parents:

3feeab2 (diff), 5265eea4 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Location:

boot/arch/arm32/src

Files:

• asm.S (modified) (2 diffs)
• main.c (modified) (2 diffs)
• mm.c (modified) (3 diffs)

boot/arch/arm32/src/asm.S

@@ -75 +75 @@
         bic     r4, r4, #(1 << CP15_C1_DC)
 
-        # Disable I-cache and Branche predictors.
+        # Disable I-cache and Branch predictors.
         bic     r4, r4, #(1 << CP15_C1_IC)
+#ifdef PROCESSOR_ARCH_armv6
         bic     r4, r4, #(1 << CP15_C1_BP)
+#endif
         
         mcr     p15, 0, r4, c1, c0, 0
 #endif
-
-
         
-        #Wait for the operations to complete
+        # Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         dsb
 #else
-        #cp15 dsb, r4 is ignored (should be zero)
+        # cp15 dsb, r4 is ignored (should be zero)
         mov r4, #0
         mcr p15, 0, r4, c7, c10, 4
@@ -98 +98 @@
         nop
 
-        #Wait for the operations to complete
+        # Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         isb
         nop
-#else
+#elif defined(PROCESSOR_ARCH_armv6)
         # cp15 isb
         mcr p15, 0, r4, c7, c5, 4

boot/arch/arm32/src/main.c

@@ -47 +47 @@
 #include <errno.h>
 #include <inflate.h>
+#include <arch/cp15.h>
 
 #define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
@@ -55 +56 @@
 static inline void clean_dcache_poc(void *address, size_t size)
 {
-        const uintptr_t addr = (uintptr_t)address;
-        for (uintptr_t a = addr; a < addr + size; a += 4) {
-                /* DCCMVAC - clean by address to the point of coherence */
-                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
+        const uintptr_t addr = (uintptr_t) address;
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+        bool sep;
+        if (MIDR_read() != CTR_read()) {
+                sep = (CTR_read() & CTR_SEP_FLAG) == CTR_SEP_FLAG;
+        } else {
+                printf("Unknown cache type.\n");
+                halt();
+        }
+#endif
+
+        for (uintptr_t a = ALIGN_DOWN(addr, CP15_C7_MVA_ALIGN); a < addr + size;
+            a += CP15_C7_MVA_ALIGN) {
+#if defined(PROCESSOR_ARCH_armv7_a)
+                DCCMVAC_write(a);
+#else
+                if (sep)
+                        DCCMVA_write(a);
+                else
+                        CCMVA_write(a);
+#endif
         }
 }

boot/arch/arm32/src/mm.c

@@ -143 +143 @@
         pte->should_be_zero_1 = 0;
         pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
-#ifdef PROCESSOR_ARCH_armv7_a
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
         /*
          * Keeps this setting in sync with memory type attributes in:
@@ -152 +152 @@
         pte->tex = section_cacheable(frame) ? 5 : 0;
         pte->cacheable = section_cacheable(frame) ? 0 : 0;
-        pte->bufferable = section_cacheable(frame) ? 1 : 0;
+        pte->bufferable = section_cacheable(frame) ? 1 : 1;
 #else
-        pte->bufferable = 1;
+        pte->bufferable = section_cacheable(frame);
         pte->cacheable = section_cacheable(frame);
         pte->tex = 0;
@@ -189 +189 @@
          */
         uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        // FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6
         val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+#endif
         TTBR0_write(val);
 }