Changes in kernel/arch/amd64/src/amd64.c [a71c158:f902d36] in mainline

File:

• kernel/arch/amd64/src/amd64.c (modified) (9 diffs)

kernel/arch/amd64/src/amd64.c

@@ -35 +35 @@
 #include <arch.h>
 
-#include <arch/types.h>
+#include <typedefs.h>
 
 #include <config.h>
@@ -67 +67 @@
 #include <ddi/irq.h>
 #include <sysinfo/sysinfo.h>
+#include <memstr.h>
 
 /** Disable I/O on non-privileged levels
@@ -121 +122 @@
         /* Enable FPU */
         cpu_setup_fpu();
-
+        
         /* Initialize segmentation */
         pm_init();
@@ -131 +132 @@
         /* Disable alignment check */
         clean_AM_flag();
-
+        
         if (config.cpu_active == 1) {
                 interrupt_init();
@@ -198 +199 @@
 void arch_post_smp_init(void)
 {
+        /* Currently the only supported platform for amd64 is 'pc'. */
+        static const char *platform = "pc";
+
+        sysinfo_set_item_data("platform", NULL, (void *) platform,
+            str_size(platform));
+
 #ifdef CONFIG_PC_KBD
         /*
@@ -211 +218 @@
                         i8042_wire(i8042_instance, kbrd);
                         trap_virtual_enable_irqs(1 << IRQ_KBD);
+                        trap_virtual_enable_irqs(1 << IRQ_MOUSE);
                 }
         }
@@ -218 +226 @@
          * self-sufficient.
          */
-        sysinfo_set_item_val("kbd", NULL, true);
-        sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
-        sysinfo_set_item_val("kbd.address.physical", NULL,
+        sysinfo_set_item_val("i8042", NULL, true);
+        sysinfo_set_item_val("i8042.inr_a", NULL, IRQ_KBD);
+        sysinfo_set_item_val("i8042.inr_b", NULL, IRQ_MOUSE);
+        sysinfo_set_item_val("i8042.address.physical", NULL,
             (uintptr_t) I8042_BASE);
-        sysinfo_set_item_val("kbd.address.kernel", NULL,
+        sysinfo_set_item_val("i8042.address.kernel", NULL,
             (uintptr_t) I8042_BASE);
 #endif
+        
+        if (irqs_info != NULL)
+                sysinfo_set_item_val(irqs_info, NULL, true);
+        
+        sysinfo_set_item_val("netif.ne2000.inr", NULL, IRQ_NE2000);
 }
 
@@ -247 +261 @@
  * we need not to go to CPL0 to read it.
  */
-unative_t sys_tls_set(unative_t addr)
+sysarg_t sys_tls_set(sysarg_t addr)
 {
         THREAD->arch.tls = addr;
         write_msr(AMD_MSR_FS, addr);
+        
         return 0;
 }
@@ -275 +290 @@
 }
 
+void irq_initialize_arch(irq_t *irq)
+{
+        (void) irq;
+}
+
 /** @}
  */