Changeset f77e591d in mainline for kernel/arch/amd64/src

Timestamp:

2010-07-14T13:05:28Z (15 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

257ceb1, 4003861

Parents:

2bf2e1d

Message:

Do not align the amd64 interrupt handlers. Give each its own unique label and
use those labels to initialize IDT. This is a similar change to the one which
went in in changeset:mainline,551.1.30 for ia32.

Location:

kernel/arch/amd64/src

Files:

• asm.S (modified) (3 diffs)
• pm.c (modified) (1 diff)

kernel/arch/amd64/src/asm.S

@@ -192 +192 @@
 #define ERROR_WORD_INTERRUPT_LIST  0x00027D00
 
-#define INTERRUPT_ALIGN         256 
-
-/** Declare interrupt handlers
- *
- * Declare interrupt handlers for n interrupt
- * vectors starting at vector i.
- *
- * The handlers call exc_dispatch().
- *
- */
-.macro handler i n
-        
+.macro handler i
+.global int_\i
+int_\i:
+
         /*
          * Choose between version with error code and version without error
-         * code. Both versions have to be of the same size. amd64 assembly is,
-         * however, a little bit tricky. For instance, subq $0x80, %rsp and
-         * subq $0x78, %rsp can result in two instructions with different
-         * op-code lengths.
-         * Therefore we align the interrupt handlers.
+         * code.
          */
         
@@ -290 +278 @@
         addq $(ISTATE_SOFT_SIZE + 8), %rsp
         iretq
-        
-        .align INTERRUPT_ALIGN
-        .if (\n - \i) - 1
-                handler "(\i + 1)", \n
-        .endif
 .endm
 
-.align INTERRUPT_ALIGN
+#define LIST_0_63 \
+        0, 1, 2, 3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,\
+        28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,\
+        53,54,55,56,57,58,59,60,61,62,63
+
 interrupt_handlers:
-        h_start:
-                handler 0 IDT_ITEMS
-        h_end:
+.irp cnt, LIST_0_63
+        handler \cnt 
+.endr
 
 /** Low-level syscall handler
@@ -545 +532 @@
         ret
 
-.data
-.global interrupt_handler_size
-
-interrupt_handler_size: .quad (h_end - h_start) / IDT_ITEMS

kernel/arch/amd64/src/pm.c

@@ -175 +175 @@
                 d->present = 1;
                 d->type = AR_INTERRUPT; /* masking interrupt */
-
-                idt_setoffset(d, ((uintptr_t) interrupt_handlers) +
-                    i * interrupt_handler_size);
         }
+
+        d = &idt[0];
+        idt_setoffset(d++, (uintptr_t) &int_0);
+        idt_setoffset(d++, (uintptr_t) &int_1);
+        idt_setoffset(d++, (uintptr_t) &int_2);
+        idt_setoffset(d++, (uintptr_t) &int_3);
+        idt_setoffset(d++, (uintptr_t) &int_4);
+        idt_setoffset(d++, (uintptr_t) &int_5);
+        idt_setoffset(d++, (uintptr_t) &int_6);
+        idt_setoffset(d++, (uintptr_t) &int_7);
+        idt_setoffset(d++, (uintptr_t) &int_8);
+        idt_setoffset(d++, (uintptr_t) &int_9);
+        idt_setoffset(d++, (uintptr_t) &int_10);
+        idt_setoffset(d++, (uintptr_t) &int_11);
+        idt_setoffset(d++, (uintptr_t) &int_12);
+        idt_setoffset(d++, (uintptr_t) &int_13);
+        idt_setoffset(d++, (uintptr_t) &int_14);
+        idt_setoffset(d++, (uintptr_t) &int_15);
+        idt_setoffset(d++, (uintptr_t) &int_16);
+        idt_setoffset(d++, (uintptr_t) &int_17);
+        idt_setoffset(d++, (uintptr_t) &int_18);
+        idt_setoffset(d++, (uintptr_t) &int_19);
+        idt_setoffset(d++, (uintptr_t) &int_20);
+        idt_setoffset(d++, (uintptr_t) &int_21);
+        idt_setoffset(d++, (uintptr_t) &int_22);
+        idt_setoffset(d++, (uintptr_t) &int_23);
+        idt_setoffset(d++, (uintptr_t) &int_24);
+        idt_setoffset(d++, (uintptr_t) &int_25);
+        idt_setoffset(d++, (uintptr_t) &int_26);
+        idt_setoffset(d++, (uintptr_t) &int_27);
+        idt_setoffset(d++, (uintptr_t) &int_28);
+        idt_setoffset(d++, (uintptr_t) &int_29);
+        idt_setoffset(d++, (uintptr_t) &int_30);
+        idt_setoffset(d++, (uintptr_t) &int_31);
+        idt_setoffset(d++, (uintptr_t) &int_32);
+        idt_setoffset(d++, (uintptr_t) &int_33);
+        idt_setoffset(d++, (uintptr_t) &int_34);
+        idt_setoffset(d++, (uintptr_t) &int_35);
+        idt_setoffset(d++, (uintptr_t) &int_36);
+        idt_setoffset(d++, (uintptr_t) &int_37);
+        idt_setoffset(d++, (uintptr_t) &int_38);
+        idt_setoffset(d++, (uintptr_t) &int_39);
+        idt_setoffset(d++, (uintptr_t) &int_40);
+        idt_setoffset(d++, (uintptr_t) &int_41);
+        idt_setoffset(d++, (uintptr_t) &int_42);
+        idt_setoffset(d++, (uintptr_t) &int_43);
+        idt_setoffset(d++, (uintptr_t) &int_44);
+        idt_setoffset(d++, (uintptr_t) &int_45);
+        idt_setoffset(d++, (uintptr_t) &int_46);
+        idt_setoffset(d++, (uintptr_t) &int_47);
+        idt_setoffset(d++, (uintptr_t) &int_48);
+        idt_setoffset(d++, (uintptr_t) &int_49);
+        idt_setoffset(d++, (uintptr_t) &int_50);
+        idt_setoffset(d++, (uintptr_t) &int_51);
+        idt_setoffset(d++, (uintptr_t) &int_52);
+        idt_setoffset(d++, (uintptr_t) &int_53);
+        idt_setoffset(d++, (uintptr_t) &int_54);
+        idt_setoffset(d++, (uintptr_t) &int_55);
+        idt_setoffset(d++, (uintptr_t) &int_56);
+        idt_setoffset(d++, (uintptr_t) &int_57);
+        idt_setoffset(d++, (uintptr_t) &int_58);
+        idt_setoffset(d++, (uintptr_t) &int_59);
+        idt_setoffset(d++, (uintptr_t) &int_60);
+        idt_setoffset(d++, (uintptr_t) &int_61);
+        idt_setoffset(d++, (uintptr_t) &int_62);
+        idt_setoffset(d++, (uintptr_t) &int_63);
 }