- Timestamp:
- 2006-03-03T00:20:31Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 09c18f78
- Parents:
- ddcf365
- Location:
- arch
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/src/fpu_context.c
rddcf365 rf76fed4 35 35 void fpu_context_save(fpu_context_t *fctx) 36 36 { 37 /* Align on 16-byte boundary */38 if (((__u64)fctx) & 0xf)39 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1);40 41 37 __asm__ volatile ( 42 38 "fxsave %0" … … 48 44 void fpu_context_restore(fpu_context_t *fctx) 49 45 { 50 /* Align on 16-byte boundary */51 if (((__u64)fctx) & 0xf)52 fctx = (fpu_context_t *)((((__u64)fctx) | 0xf) + 1);53 46 __asm__ volatile ( 54 47 "fxrstor %0" … … 57 50 } 58 51 59 void fpu_init( fpu_context_t *fctx)52 void fpu_init() 60 53 { 61 54 /* TODO: Zero all SSE, MMX etc. registers */ -
arch/ia32/include/fpu_context.h
rddcf365 rf76fed4 32 32 #include <arch/types.h> 33 33 34 #define ARCH_HAS_FPU 35 #define FPU_CONTEXT_ALIGN 16 36 34 37 struct fpu_context { 35 38 /* TODO: We need malloc that aligns structures on 16-byte boundary */ 36 __u8 fpu[512 +16]; /* FXSAVE & FXRSTOR storage area */39 __u8 fpu[512]; /* FXSAVE & FXRSTOR storage area */ 37 40 }; 38 41 -
arch/ia32/src/fpu_context.c
rddcf365 rf76fed4 49 49 } 50 50 51 void fpu_init( fpu_context_t *fctx)51 void fpu_init() 52 52 { 53 53 __asm__ volatile ( -
arch/mips32/include/fpu_context.h
rddcf365 rf76fed4 32 32 #include <arch/types.h> 33 33 34 #define ARCH_HAS_FPU 35 #define FPU_CONTEXT_ALIGN sizeof(__native) 36 34 37 struct fpu_context { 35 38 __native dregs[32]; -
arch/mips32/src/fpu_context.c
rddcf365 rf76fed4 51 51 } 52 52 53 void fpu_init( fpu_context_t *fctx)53 void fpu_init() 54 54 { 55 55 /* TODO: Zero all registers */
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