Changeset f6cf76f in mainline for kernel/arch/mips32
- Timestamp:
- 2019-04-05T18:30:19Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 29beac8
- Parents:
- f4bb404
- Location:
- kernel/arch/mips32
- Files:
-
- 2 edited
-
include/arch/mach/malta/malta.h (modified) (1 diff)
-
src/mach/malta/malta.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/mips32/include/arch/mach/malta/malta.h
rf4bb404 rf6cf76f 45 45 46 46 #define PIC0_BASE (MALTA_PCI_BASE + 0x20) 47 #define PIC0_SPURIOUS_IRQ 7 47 48 #define PIC1_BASE (MALTA_PCI_BASE + 0xa0) 49 #define PIC1_SPURIOUS_IRQ 15 48 50 49 51 #define ISA_IRQ_COUNT 16 -
kernel/arch/mips32/src/mach/malta/malta.c
rf4bb404 rf6cf76f 74 74 { 75 75 uint8_t isa_irq = host2uint32_t_le(pio_read_32(GT64120_PCI0_INTACK)); 76 if (isa_irq == PIC0_SPURIOUS_IRQ || isa_irq == PIC1_SPURIOUS_IRQ) { 77 /* 78 * XXX: Examine ISR to figure out whether this is indeed a 79 * spurious or actual IRQ. 80 */ 81 #ifdef CONFIG_DEBUG 82 log(LF_ARCH, LVL_DEBUG, "cpu%u: PIC spurious interrupt", 83 CPU->id); 84 return; 85 #endif 86 } 76 87 irq_t *irq = irq_dispatch_and_lock(isa_irq); 77 88 if (irq) {
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