Changeset f47fd19 in mainline for kernel/arch/sparc64/include/trap

Timestamp:

2006-08-21T13:36:34Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a7961271

Parents:

ee289cf0

Message:

sparc64 work.
Define the istate structure.
Move the identity-mapping handler to assembly.
Make the preemptible handler more general so that TL=1 MMU exceptions can make use of it.

Little bit of formatting and indentation.

Location:

kernel/arch/sparc64/include/trap

Files:

• interrupt.h (modified) (1 diff)
• mmu.h (modified) (2 diffs)
• trap_table.h (modified) (1 diff)

kernel/arch/sparc64/include/trap/interrupt.h

@@ -82 +82 @@
         save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
         mov \n - 1, %o0
-        mov %fp, %o1
         PREEMPTIBLE_HANDLER exc_dispatch
 .endm

kernel/arch/sparc64/include/trap/mmu.h

@@ -39 +39 @@
 
 #include <arch/stack.h>
+#include <arch/mm/tlb.h>
+#include <arch/mm/mmu.h>
+#include <arch/mm/tte.h>
 
 #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS     0x64
@@ -56 +59 @@
 
 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
-        save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
-        call fast_data_access_mmu_miss
-        nop
-        restore
+        /*
+         * First, test if it is the portion of the kernel address space
+         * which is faulting. If that is the case, immediately create
+         * identity mapping for that page in DTLB. VPN 0 is excluded from
+         * this treatment.
+         *
+         * Note that branch-delay slots are used in order to save space.
+         */
+        mov VA_DMMU_TAG_ACCESS, %g1
+        ldxa [%g1] ASI_DMMU, %g1                        ! read the faulting Context and VPN
+        set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
+        andcc %g1, %g2, %g3                             ! get Context
+        bnz 0f                                          ! Context is non-zero
+        andncc %g1, %g2, %g3                            ! get page address into %g3
+        bz 0f                                           ! page address is zero
+
+        /*
+         * Create and insert the identity-mapped entry for
+         * the faulting kernel page.
+         */
+        
+        or %g3, (TTE_CP|TTE_P|TTE_W), %g2               ! 8K pages are the default (encoded as 0)
+        set 1, %g3
+        sllx %g3, TTE_V_SHIFT, %g3
+        or %g2, %g3, %g2
+        stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
         retry
+
+0:
+        save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp                                             
+        PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
 .endm
 

kernel/arch/sparc64/include/trap/trap_table.h

@@ -78 +78 @@
 .endm
 
+/*
+ * The following needs to be in sync with the
+ * definition of the istate structure.
+ */
 #define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE    (STACK_WINDOW_SAVE_AREA_SIZE+(4*8))
 #define SAVED_TSTATE    -(1*8)