Changeset f2ea5d8 in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2006-11-17T20:21:25Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f18cc64
Parents:
282f2c9c
Message:

sparc64 code to support physical memory that starts on non-zero addresses.
Still needs to be tested on systems with such setup.

Location:
kernel/arch/sparc64/include
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/boot/boot.h

    r282f2c9c rf2ea5d8  
    7676 */
    7777typedef struct {
     78        uintptr_t physmem_start;
    7879        taskmap_t taskmap;
    7980        memmap_t memmap;

  • kernel/arch/sparc64/include/mm/page.h

    r282f2c9c rf2ea5d8  
    4949#include <genarch/mm/page_ht.h>
    5050
    51 #define KA2PA(x)        ((uintptr_t) (x))
    52 #define PA2KA(x)        ((uintptr_t) (x))
     51extern uintptr_t physmem_base;
     52
     53#define KA2PA(x)        (((uintptr_t) (x)) + physmem_base)
     54#define PA2KA(x)        (((uintptr_t) (x)) - physmem_base)
    5355
    5456union page_address {

  • kernel/arch/sparc64/include/trap/mmu.h

    r282f2c9c rf2ea5d8  
    112112        bz 0f                                           ! page address is zero
    113113
    114         or %g3, (TTE_CV|TTE_CP|TTE_P|TTE_W), %g2        ! 8K pages are the default (encoded as 0)
    115         mov 1, %g3
    116         sllx %g3, TTE_V_SHIFT, %g3
    117         or %g2, %g3, %g2
     114        sethi %hi(kernel_8k_tlb_data_template), %g2
     115        ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2
     116        or %g3, %g2, %g2
    118117        stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
    119118        retry
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