Index: kernel/arch/ia32/src/drivers/i8259.c
===================================================================
--- kernel/arch/ia32/src/drivers/i8259.c	(revision c5396c1804ab53d2d15266e72be0b0617bebb8b3)
+++ kernel/arch/ia32/src/drivers/i8259.c	(revision ee95794cc751c58d26c309eb02e2009401377b58)
@@ -42,5 +42,5 @@
 #include <arch/asm.h>
 #include <arch.h>
-#include <print.h>
+#include <log.h>
 #include <interrupt.h>
 
@@ -129,5 +129,5 @@
 {
 #ifdef CONFIG_DEBUG
-	printf("cpu%u: PIC spurious interrupt\n", CPU->id);
+	log(LF_ARCH, LVL_DEBUG, "cpu%u: PIC spurious interrupt", CPU->id);
 #endif
 }
Index: kernel/arch/ia32/src/smp/apic.c
===================================================================
--- kernel/arch/ia32/src/smp/apic.c	(revision c5396c1804ab53d2d15266e72be0b0617bebb8b3)
+++ kernel/arch/ia32/src/smp/apic.c	(revision ee95794cc751c58d26c309eb02e2009401377b58)
@@ -42,5 +42,5 @@
 #include <interrupt.h>
 #include <arch/interrupt.h>
-#include <print.h>
+#include <log.h>
 #include <arch/asm.h>
 #include <arch.h>
@@ -135,5 +135,5 @@
 {
 #ifdef CONFIG_DEBUG
-	printf("cpu%u: APIC spurious interrupt\n", CPU->id);
+	log(LF_ARCH, LVL_DEBUG, "cpu%u: APIC spurious interrupt", CPU->id);
 #endif
 }
@@ -241,18 +241,23 @@
 	esr.value = l_apic[ESR];
 	
-	if (esr.send_checksum_error)
-		printf("Send Checksum Error\n");
-	if (esr.receive_checksum_error)
-		printf("Receive Checksum Error\n");
-	if (esr.send_accept_error)
-		printf("Send Accept Error\n");
-	if (esr.receive_accept_error)
-		printf("Receive Accept Error\n");
-	if (esr.send_illegal_vector)
-		printf("Send Illegal Vector\n");
-	if (esr.received_illegal_vector)
-		printf("Received Illegal Vector\n");
-	if (esr.illegal_register_address)
-		printf("Illegal Register Address\n");
+	if (esr.err_bitmap) {
+		log_begin(LF_ARCH, LVL_ERROR);
+		log_printf("APIC errors detected:");
+		if (esr.send_checksum_error)
+			log_printf("\nSend Checksum Error");
+		if (esr.receive_checksum_error)
+			log_printf("\nReceive Checksum Error");
+		if (esr.send_accept_error)
+			log_printf("\nSend Accept Error");
+		if (esr.receive_accept_error)
+			log_printf("\nReceive Accept Error");
+		if (esr.send_illegal_vector)
+			log_printf("\nSend Illegal Vector");
+		if (esr.received_illegal_vector)
+			log_printf("\nReceived Illegal Vector");
+		if (esr.illegal_register_address)
+			log_printf("\nIllegal Register Address");
+		log_end();
+	}
 	
 	return !esr.err_bitmap;
@@ -270,5 +275,5 @@
 			retries = 0;
 #ifdef CONFIG_DEBUG
-			printf("IPI is pending.\n");
+			log(LF_ARCH, LVL_DEBUG, "IPI is pending.");
 #endif
 			delay(20);
@@ -489,10 +494,11 @@
 {
 #ifdef LAPIC_VERBOSE
-	printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
+	log_begin(LF_ARCH, LVL_DEBUG);
+	log_printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
 	    CPU->id, l_apic_id());
 	
 	lvt_tm_t tm;
 	tm.value = l_apic[LVT_Tm];
-	printf("LVT Tm: vector=%" PRIu8 ", %s, %s, %s\n",
+	log_printf("LVT Tm: vector=%" PRIu8 ", %s, %s, %s\n",
 	    tm.vector, delivs_str[tm.delivs], mask_str[tm.masked],
 	    tm_mode_str[tm.mode]);
@@ -500,5 +506,5 @@
 	lvt_lint_t lint;
 	lint.value = l_apic[LVT_LINT0];
-	printf("LVT LINT0: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
+	log_printf("LVT LINT0: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
 	    tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
 	    intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
@@ -506,5 +512,5 @@
 	
 	lint.value = l_apic[LVT_LINT1];
-	printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
+	log_printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
 	    tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
 	    intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
@@ -513,6 +519,7 @@
 	lvt_error_t error;
 	error.value = l_apic[LVT_Err];
-	printf("LVT Err: vector=%" PRIu8 ", %s, %s\n", error.vector,
+	log_printf("LVT Err: vector=%" PRIu8 ", %s, %s\n", error.vector,
 	    delivs_str[error.delivs], mask_str[error.masked]);
+	log_end();
 #endif
 }
Index: kernel/arch/ia32/src/smp/mps.c
===================================================================
--- kernel/arch/ia32/src/smp/mps.c	(revision c5396c1804ab53d2d15266e72be0b0617bebb8b3)
+++ kernel/arch/ia32/src/smp/mps.c	(revision ee95794cc751c58d26c309eb02e2009401377b58)
@@ -36,5 +36,5 @@
 
 #include <config.h>
-#include <print.h>
+#include <log.h>
 #include <debug.h>
 #include <arch/smp/mps.h>
@@ -181,5 +181,5 @@
 	buf[6] = 0;
 	
-	printf("MPS: bus=%" PRIu8 " (%s)\n", bus->bus_id, buf);
+	log(LF_ARCH, LVL_DEBUG, "MPS: bus=%" PRIu8 " (%s)", bus->bus_id, buf);
 #endif
 }
@@ -205,58 +205,60 @@
 {
 #ifdef MPSCT_VERBOSE
-	printf("MPS: ");
+	log_begin(LF_ARCH, LVL_DEBUG);
+	log_printf("MPS: ");
 	
 	switch (iointr->intr_type) {
 	case 0:
-		printf("INT");
-		break;
-	case 1:
-		printf("NMI");
-		break;
-	case 2:
-		printf("SMI");
-		break;
-	case 3:
-		printf("ExtINT");
-		break;
-	}
-	
-	printf(", ");
+		log_printf("INT");
+		break;
+	case 1:
+		log_printf("NMI");
+		break;
+	case 2:
+		log_printf("SMI");
+		break;
+	case 3:
+		log_printf("ExtINT");
+		break;
+	}
+	
+	log_printf(", ");
 	
 	switch (iointr->poel & 3) {
 	case 0:
-		printf("bus-like");
-		break;
-	case 1:
-		printf("active high");
-		break;
-	case 2:
-		printf("reserved");
-		break;
-	case 3:
-		printf("active low");
-		break;
-	}
-	
-	printf(", ");
+		log_printf("bus-like");
+		break;
+	case 1:
+		log_printf("active high");
+		break;
+	case 2:
+		log_printf("reserved");
+		break;
+	case 3:
+		log_printf("active low");
+		break;
+	}
+	
+	log_printf(", ");
 	
 	switch ((iointr->poel >> 2) & 3) {
 	case 0:
-		printf("bus-like");
-		break;
-	case 1:
-		printf("edge-triggered");
-		break;
-	case 2:
-		printf("reserved");
-		break;
-	case 3:
-		printf("level-triggered");
-		break;
-	}
-	
-	printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8" pin=%"
-	    PRIu8 "\n", iointr->src_bus_id, iointr->src_bus_irq,
+		log_printf("bus-like");
+		break;
+	case 1:
+		log_printf("edge-triggered");
+		break;
+	case 2:
+		log_printf("reserved");
+		break;
+	case 3:
+		log_printf("level-triggered");
+		break;
+	}
+	
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8" pin=%"
+	    PRIu8, iointr->src_bus_id, iointr->src_bus_irq,
 	    iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
+	log_end();
 #endif
 }
@@ -266,58 +268,60 @@
 {
 #ifdef MPSCT_VERBOSE
-	printf("MPS: ");
+	log_begin(LF_ARCH, LVL_DEBUG);
+	log_printf("MPS: ");
 	
 	switch (lintr->intr_type) {
 	case 0:
-		printf("INT");
-		break;
-	case 1:
-		printf("NMI");
-		break;
-	case 2:
-		printf("SMI");
-		break;
-	case 3:
-		printf("ExtINT");
-		break;
-	}
-	
-	printf(", ");
+		log_printf("INT");
+		break;
+	case 1:
+		log_printf("NMI");
+		break;
+	case 2:
+		log_printf("SMI");
+		break;
+	case 3:
+		log_printf("ExtINT");
+		break;
+	}
+	
+	log_printf(", ");
 	
 	switch (lintr->poel & 3) {
 	case 0:
-		printf("bus-like");
-		break;
-	case 1:
-		printf("active high");
-		break;
-	case 2:
-		printf("reserved");
-		break;
-	case 3:
-		printf("active low");
-		break;
-	}
-	
-	printf(", ");
+		log_printf("bus-like");
+		break;
+	case 1:
+		log_printf("active high");
+		break;
+	case 2:
+		log_printf("reserved");
+		break;
+	case 3:
+		log_printf("active low");
+		break;
+	}
+	
+	log_printf(", ");
 	
 	switch ((lintr->poel >> 2) & 3) {
 	case 0:
-		printf("bus-like");
-		break;
-	case 1:
-		printf("edge-triggered");
-		break;
-	case 2:
-		printf("reserved");
-		break;
-	case 3:
-		printf("level-triggered");
-		break;
-	}
-	
-	printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8" pin=%"
-	    PRIu8 "\n", lintr->src_bus_id, lintr->src_bus_irq,
+		log_printf("bus-like");
+		break;
+	case 1:
+		log_printf("edge-triggered");
+		break;
+	case 2:
+		log_printf("reserved");
+		break;
+	case 3:
+		log_printf("level-triggered");
+		break;
+	}
+	
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8" pin=%"
+	    PRIu8, lintr->src_bus_id, lintr->src_bus_irq,
 	    lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
+	log_end();
 #endif
 }
@@ -332,6 +336,7 @@
 		switch (cur[CT_EXT_ENTRY_TYPE]) {
 		default:
-			printf("MPS: Skipping MP Configuration Table extended "
-			    "entry type %" PRIu8 "\n", cur[CT_EXT_ENTRY_TYPE]);
+			log(LF_ARCH, LVL_NOTE, "MPS: Skipping MP Configuration"
+			    " Table extended entry type %" PRIu8,
+			    cur[CT_EXT_ENTRY_TYPE]);
 		}
 	}
@@ -341,15 +346,15 @@
 {
 	if (ct->signature != CT_SIGNATURE) {
-		printf("MPS: Wrong ct->signature\n");
+		log(LF_ARCH, LVL_WARN, "MPS: Wrong ct->signature");
 		return;
 	}
 	
 	if (!mps_ct_check()) {
-		printf("MPS: Wrong ct checksum\n");
+		log(LF_ARCH, LVL_WARN, "MPS: Wrong ct checksum");
 		return;
 	}
 	
 	if (ct->oem_table) {
-		printf("MPS: ct->oem_table not supported\n");
+		log(LF_ARCH, LVL_WARN, "MPS: ct->oem_table not supported");
 		return;
 	}
@@ -402,5 +407,5 @@
 			 * Something is wrong. Fallback to UP mode.
 			 */
-			printf("MPS: ct badness %" PRIu8 "\n", *cur);
+			log(LF_ARCH, LVL_WARN, "MPS: ct badness %" PRIu8, *cur);
 			return;
 		}
@@ -418,5 +423,5 @@
 	 * Not yet implemented.
 	 */
-	printf("MPS: Default configuration not supported\n");
+	log(LF_ARCH, LVL_WARN, "MPS: Default configuration not supported");
 }
 
@@ -449,9 +454,9 @@
 	
 fs_found:
-	printf("%p: MPS Floating Pointer Structure\n", fs);
+	log(LF_ARCH, LVL_NOTE, "%p: MPS Floating Pointer Structure", fs);
 	
 	if ((fs->config_type == 0) && (fs->configuration_table)) {
 		if (fs->mpfib2 >> 7) {
-			printf("MPS: PIC mode not supported\n");
+			log(LF_ARCH, LVL_WARN, "MPS: PIC mode not supported\n");
 			return;
 		}
Index: kernel/arch/ia32/src/smp/smp.c
===================================================================
--- kernel/arch/ia32/src/smp/smp.c	(revision c5396c1804ab53d2d15266e72be0b0617bebb8b3)
+++ kernel/arch/ia32/src/smp/smp.c	(revision ee95794cc751c58d26c309eb02e2009401377b58)
@@ -52,5 +52,5 @@
 #include <mm/slab.h>
 #include <mm/as.h>
-#include <print.h>
+#include <log.h>
 #include <memstr.h>
 #include <arch/drivers/i8259.h>
@@ -129,6 +129,6 @@
 		
 		if (ops->cpu_apic_id(i) == bsp_l_apic) {
-			printf("kmp: bad processor entry #%u, will not send IPI "
-			    "to myself\n", i);
+			log(LF_ARCH, LVL_ERROR, "kmp: bad processor entry #%u, "
+			    "will not send IPI to myself", i);
 			continue;
 		}
@@ -162,10 +162,10 @@
 			if (waitq_sleep_timeout(&ap_completion_wq, 1000000,
 			    SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) {
-				printf("%s: waiting for cpu%u (APIC ID = %d) "
-				    "timed out\n", __FUNCTION__, i,
-				    ops->cpu_apic_id(i));
+				log(LF_ARCH, LVL_NOTE, "%s: waiting for cpu%u "
+				    "(APIC ID = %d) timed out", __FUNCTION__,
+				    i, ops->cpu_apic_id(i));
 			}
 		} else
-			printf("INIT IPI for l_apic%d failed\n",
+			log(LF_ARCH, LVL_ERROR, "INIT IPI for l_apic%d failed",
 			    ops->cpu_apic_id(i));
 	}
