Changeset ee06f2a in mainline for kernel/arch/ia32

Timestamp:

2009-02-15T15:28:00Z (17 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2d96f4d

Parents:

e7f2ad68

Message:

Introduce a more platform-neutral name for programmed I/O.

The new API looks like pio_read_n() or pio_write_n(), where n is 8, 16 or 32.
The old API (i.e. inb(), inw(), inl(), outb() outw(), outl()) may have made
some people think that the interface is only to be used with the separate I/O
space. That's not the case. This API is to be implemented on all platforms
so that we can finally have really generic kernel device drivers.

Location:

kernel/arch/ia32

Files:

• include/asm.h (modified) (6 diffs)
• include/drivers/i8042.h (modified) (1 diff)
• src/drivers/i8254.c (modified) (2 diffs)
• src/drivers/i8259.c (modified) (4 diffs)
• src/smp/smp.c (modified) (1 diff)

kernel/arch/ia32/include/asm.h

@@ -106 +106 @@
  * @param val Value to write
  */
-static inline void outb(uint16_t port, uint8_t val)
+static inline void pio_write_8(uint16_t port, uint8_t val)
 {
         asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) );
@@ -118 +118 @@
  * @param val Value to write
  */
-static inline void outw(uint16_t port, uint16_t val)
+static inline void pio_write_16(uint16_t port, uint16_t val)
 {
         asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) );
@@ -130 +130 @@
  * @param val Value to write
  */
-static inline void outl(uint16_t port, uint32_t val)
+static inline void pio_write_32(uint16_t port, uint32_t val)
 {
         asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) );
@@ -142 +142 @@
  * @return Value read
  */
-static inline uint8_t inb(uint16_t port)
+static inline uint8_t pio_read_8(uint16_t port)
 {
         uint8_t val;
@@ -157 +157 @@
  * @return Value read
  */
-static inline uint16_t inw(uint16_t port)
+static inline uint16_t pio_read_16(uint16_t port)
 {
         uint16_t val;
@@ -172 +172 @@
  * @return Value read
  */
-static inline uint32_t inl(uint16_t port)
+static inline uint32_t pio_read_32(uint16_t port)
 {
         uint32_t val;

kernel/arch/ia32/include/drivers/i8042.h

@@ -48 +48 @@
 static inline void i8042_data_write(uint8_t data)
 {
-        outb(i8042_DATA, data);
+        pio_write_8(i8042_DATA, data);
 }
 
 static inline uint8_t i8042_data_read(void)
 {
-        return inb(i8042_DATA);
+        return pio_read_8(i8042_DATA);
 }
 
 static inline uint8_t i8042_status_read(void)
 {
-        return inb(i8042_STATUS);
+        return pio_read_8(i8042_STATUS);
 }
 
 static inline void i8042_command_write(uint8_t command)
 {
-        outb(i8042_STATUS, command);
+        pio_write_8(i8042_STATUS, command);
 }
 

kernel/arch/ia32/src/drivers/i8254.c

@@ -95 +95 @@
 void i8254_normal_operation(void)
 {
-        outb(CLK_PORT4, 0x36);
+        pio_write_8(CLK_PORT4, 0x36);
         pic_disable_irqs(1 << IRQ_CLK);
-        outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
-        outb(CLK_PORT1, (CLK_CONST / HZ) >> 8);
+        pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
+        pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8);
         pic_enable_irqs(1 << IRQ_CLK);
 }
@@ -115 +115 @@
          * MAGIC_NUMBER is the magic value for 1ms.
          */
-        outb(CLK_PORT4, 0x30);
-        outb(CLK_PORT1, 0xff);
-        outb(CLK_PORT1, 0xff);
+        pio_write_8(CLK_PORT4, 0x30);
+        pio_write_8(CLK_PORT1, 0xff);
+        pio_write_8(CLK_PORT1, 0xff);
 
         do {
                 /* will read both status and count */
-                outb(CLK_PORT4, 0xc2);
-                not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1);
-                t1 = inb(CLK_PORT1);
-                t1 |= inb(CLK_PORT1) << 8;
+                pio_write_8(CLK_PORT4, 0xc2);
+                not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1);
+                t1 = pio_read_8(CLK_PORT1);
+                t1 |= pio_read_8(CLK_PORT1) << 8;
         } while (not_ok);
 
         asm_delay_loop(LOOPS);
 
-        outb(CLK_PORT4, 0xd2);
-        t2 = inb(CLK_PORT1);
-        t2 |= inb(CLK_PORT1) << 8;
+        pio_write_8(CLK_PORT4, 0xd2);
+        t2 = pio_read_8(CLK_PORT1);
+        t2 |= pio_read_8(CLK_PORT1) << 8;
 
         /*
          * We want to determine the overhead of the calibrating mechanism.
          */
-        outb(CLK_PORT4, 0xd2);
-        o1 = inb(CLK_PORT1);
-        o1 |= inb(CLK_PORT1) << 8;
+        pio_write_8(CLK_PORT4, 0xd2);
+        o1 = pio_read_8(CLK_PORT1);
+        o1 |= pio_read_8(CLK_PORT1) << 8;
 
         asm_fake_loop(LOOPS);
 
-        outb(CLK_PORT4, 0xd2);
-        o2 = inb(CLK_PORT1);
-        o2 |= inb(CLK_PORT1) << 8;
+        pio_write_8(CLK_PORT4, 0xd2);
+        o2 = pio_read_8(CLK_PORT1);
+        o2 |= pio_read_8(CLK_PORT1) << 8;
 
         CPU->delay_loop_const =

kernel/arch/ia32/src/drivers/i8259.c

@@ -50 +50 @@
 {
         /* ICW1: this is ICW1, ICW4 to follow */
-        outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
+        pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
 
         /* ICW2: IRQ 0 maps to INT IRQBASE */
-        outb(PIC_PIC0PORT2, IVT_IRQBASE);
+        pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE);
 
         /* ICW3: pic1 using IRQ IRQ_PIC1 */
-        outb(PIC_PIC0PORT2, 1 << IRQ_PIC1);
+        pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1);
 
         /* ICW4: i8086 mode */
-        outb(PIC_PIC0PORT2, 1);
+        pio_write_8(PIC_PIC0PORT2, 1);
 
         /* ICW1: ICW1, ICW4 to follow */
-        outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
+        pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
 
         /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
-        outb(PIC_PIC1PORT2, IVT_IRQBASE + 8);
+        pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8);
 
         /* ICW3: pic1 is known as IRQ_PIC1 */
-        outb(PIC_PIC1PORT2, IRQ_PIC1);
+        pio_write_8(PIC_PIC1PORT2, IRQ_PIC1);
 
         /* ICW4: i8086 mode */
-        outb(PIC_PIC1PORT2, 1);
+        pio_write_8(PIC_PIC1PORT2, 1);
 
         /*
@@ -95 +95 @@
 
         if (irqmask & 0xff) {
-                x = inb(PIC_PIC0PORT2);
-                outb(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
+                x = pio_read_8(PIC_PIC0PORT2);
+                pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
         }
         if (irqmask >> 8) {
-                x = inb(PIC_PIC1PORT2);
-                outb(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
+                x = pio_read_8(PIC_PIC1PORT2);
+                pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
         }
 }
@@ -109 +109 @@
 
         if (irqmask & 0xff) {
-                x = inb(PIC_PIC0PORT2);
-                outb(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
+                x = pio_read_8(PIC_PIC0PORT2);
+                pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
         }
         if (irqmask >> 8) {
-                x = inb(PIC_PIC1PORT2);
-                outb(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
+                x = pio_read_8(PIC_PIC1PORT2);
+                pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
         }
 }
@@ -120 +120 @@
 void pic_eoi(void)
 {
-        outb(0x20, 0x20);
-        outb(0xa0, 0x20);
+        pio_write_8(0x20, 0x20);
+        pio_write_8(0xa0, 0x20);
 }
 

kernel/arch/ia32/src/smp/smp.c

@@ -123 +123 @@
          * BIOS will not do the POST after the INIT signal.
          */
-        outb(0x70, 0xf);
-        outb(0x71, 0xa);
+        pio_write_8(0x70, 0xf);
+        pio_write_8(0x71, 0xa);
 
         pic_disable_irqs(0xffff);