Changeset ed166f7 in mainline for kernel/arch/sparc64/src/mm

Timestamp:

2006-08-31T18:53:14Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6767c1d

Parents:

e0b241f

Message:

A lot of untested sparc64 stuff:

• Write ASID to hardware when a thread is about to run in userspace.
• Add userspace() and switch_to_userspace() functions.
• Handle special cases when the userspace spill/fill handler causes MMU trap.
• Resolve some TODOs in the existing sparc64 code.
• sparc64 has now C99 compliant header guards.
• Formatting and indentation fixes.

Location:

kernel/arch/sparc64/src/mm

Files:

• as.c (modified) (3 diffs)
• tlb.c (modified) (2 diffs)

kernel/arch/sparc64/src/mm/as.c

@@ -27 +27 @@
  */
 
- /** @addtogroup sparc64mm
+/** @addtogroup sparc64mm
  * @{
  */
@@ -34 +34 @@
 
 #include <arch/mm/as.h>
+#include <arch/mm/tlb.h>
 #include <genarch/mm/as_ht.h>
 #include <genarch/mm/asid_fifo.h>
@@ -44 +45 @@
 }
 
- /** @}
+void as_install_arch(as_t *as)
+{
+        tlb_context_reg_t ctx;
+        
+        /*
+         * Write ASID to secondary context register.
+         * The primary context register has to be set
+         * from TL>0 so it will be filled from the
+         * secondary context register from the TL=1
+         * code just before switch to userspace.
+         */
+        ctx.v = 0;
+        ctx.context = as->asid;
+        mmu_secondary_context_write(ctx.v);
+}
+
+/** @}
  */
 

kernel/arch/sparc64/src/mm/tlb.c

@@ -375 +375 @@
 void tlb_invalidate_asid(asid_t asid)
 {
-        /* TODO: write asid to some Context register and encode the register in second parameter below. */
-        itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
-        dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
+        tlb_context_reg_t sc_save, ctx;
+        
+        ctx.v = sc_save.v = mmu_secondary_context_read();
+        ctx.context = asid;
+        mmu_secondary_context_write(ctx.v);
+        
+        itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
+        dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
+        
+        mmu_secondary_context_write(sc_save.v);
 }
 
@@ -389 +396 @@
 {
         int i;
+        tlb_context_reg_t sc_save, ctx;
+        
+        ctx.v = sc_save.v = mmu_secondary_context_read();
+        ctx.context = asid;
+        mmu_secondary_context_write(ctx.v);
         
         for (i = 0; i < cnt; i++) {
-                /* TODO: write asid to some Context register and encode the register in second parameter below. */
-                itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
-                dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
-        }
+                itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
+                dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
+        }
+        
+        mmu_secondary_context_write(sc_save.v);
 }