Changeset ed166f7 in mainline for kernel/arch/sparc64/src


Ignore:
Timestamp:
2006-08-31T18:53:14Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6767c1d
Parents:
e0b241f
Message:

A lot of untested sparc64 stuff:

  • Write ASID to hardware when a thread is about to run in userspace.
  • Add userspace() and switch_to_userspace() functions.
  • Handle special cases when the userspace spill/fill handler causes MMU trap.
  • Resolve some TODOs in the existing sparc64 code.
  • sparc64 has now C99 compliant header guards.
  • Formatting and indentation fixes.
Location:
kernel/arch/sparc64/src
Files:
9 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/src/asm.S

    re0b241f red166f7  
    2929#include <arch/stack.h>
    3030#include <arch/regdef.h>
     31#include <arch/mm/mmu.h>
    3132
    3233.text
    … …  
    144145read_from_ag_g7:
    145146        READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
     147
     148
     149/** Switch to userspace.
     150 *
     151 * %o0  Userspace entry address.
     152 * %o1  Userspace stack pointer address.
     153 */
     154.global switch_to_userspace
     155switch_to_userspace:
     156        flushw
     157        wrpr %g0, 0, %cleanwin          ! avoid information leak
     158        save %o1, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
     159
     160        clr %i2
     161        clr %i3
     162        clr %i4
     163        clr %i5
     164        clr %i6
     165
     166        wrpr %g0, 1, %tl                ! enforce mapping via nucleus
     167
     168        rdpr %cwp, %g1
     169        wrpr %g1, TSTATE_IE_BIT, %tstate
     170        wrpr %i0, 0, %tnpc
     171       
     172        /*
     173         * Set primary context according to secondary context.
     174         * Secondary context has been already installed by
     175         * higher-level functions.
     176         */
     177        wr %g0, ASI_DMMU, %asi
     178        ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1
     179        stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi
     180        flush %i7
     181       
     182        done                            ! jump to userspace

  • kernel/arch/sparc64/src/ddi/ddi.c

    re0b241f red166f7  
    2727 */
    2828
    29  /** @addtogroup sparc64ddi
     29/** @addtogroup sparc64ddi
    3030 * @{
    3131 */
    … …  
    5353}
    5454
    55  /** @}
     55/** @}
    5656 */
    57 

  • kernel/arch/sparc64/src/dummy.s

    re0b241f red166f7  
    4040.global fpu_enable
    4141.global fpu_init
    42 .global userspace
    4342.global sys_tls_set
    4443
    … …  
    5655fpu_enable:
    5756fpu_init:
    58 userspace:
    5957sys_tls_set:
    6058

  • kernel/arch/sparc64/src/mm/as.c

    re0b241f red166f7  
    2727 */
    2828
    29  /** @addtogroup sparc64mm
     29/** @addtogroup sparc64mm
    3030 * @{
    3131 */
    … …  
    3434
    3535#include <arch/mm/as.h>
     36#include <arch/mm/tlb.h>
    3637#include <genarch/mm/as_ht.h>
    3738#include <genarch/mm/asid_fifo.h>
    … …  
    4445}
    4546
    46  /** @}
     47void as_install_arch(as_t *as)
     48{
     49        tlb_context_reg_t ctx;
     50       
     51        /*
     52         * Write ASID to secondary context register.
     53         * The primary context register has to be set
     54         * from TL>0 so it will be filled from the
     55         * secondary context register from the TL=1
     56         * code just before switch to userspace.
     57         */
     58        ctx.v = 0;
     59        ctx.context = as->asid;
     60        mmu_secondary_context_write(ctx.v);
     61}
     62
     63/** @}
    4764 */
    4865

  • kernel/arch/sparc64/src/mm/tlb.c

    re0b241f red166f7  
    375375void tlb_invalidate_asid(asid_t asid)
    376376{
    377         /* TODO: write asid to some Context register and encode the register in second parameter below. */
    378         itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
    379         dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
     377        tlb_context_reg_t sc_save, ctx;
     378       
     379        ctx.v = sc_save.v = mmu_secondary_context_read();
     380        ctx.context = asid;
     381        mmu_secondary_context_write(ctx.v);
     382       
     383        itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
     384        dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
     385       
     386        mmu_secondary_context_write(sc_save.v);
    380387}
    381388
    … …  
    389396{
    390397        int i;
     398        tlb_context_reg_t sc_save, ctx;
     399       
     400        ctx.v = sc_save.v = mmu_secondary_context_read();
     401        ctx.context = asid;
     402        mmu_secondary_context_write(ctx.v);
    391403       
    392404        for (i = 0; i < cnt; i++) {
    393                 /* TODO: write asid to some Context register and encode the register in second parameter below. */
    394                 itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    395                 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
    396         }
     405                itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
     406                dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
     407        }
     408       
     409        mmu_secondary_context_write(sc_save.v);
    397410}
    398411

  • kernel/arch/sparc64/src/proc/scheduler.c

    re0b241f red166f7  
    9292                 * in the userspace window buffer to %g7 in the alternate and interrupt sets.
    9393                 */
    94                 write_to_ig_g6((uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS);
    95                 write_to_ag_g6((uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS);
     94                uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE
     95                        - (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT));
     96                write_to_ig_g6(sp);
     97                write_to_ag_g6(sp);
    9698                write_to_ag_g7((uintptr_t) THREAD->arch.uspace_window_buffer);
    9799        }

  • kernel/arch/sparc64/src/sparc64.c

    re0b241f red166f7  
    3535#include <arch.h>
    3636#include <debug.h>
     37#include <config.h>
    3738#include <arch/trap/trap.h>
    3839#include <arch/console.h>
    … …  
    4243#include <arch/boot/boot.h>
    4344#include <arch/arch.h>
    44 #include <arch/mm/tlb.h>
    45 #include <mm/asid.h>
     45#include <arch/mm/page.h>
     46#include <arch/stack.h>
     47#include <userspace.h>
    4648
    4749bootinfo_t bootinfo;
    … …  
    9294}
    9395
     96/** Switch to userspace. */
     97void userspace(uspace_arg_t *kernel_uarg)
     98{
     99        switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry,
     100                ((uintptr_t) kernel_uarg->uspace_stack) + STACK_SIZE
     101                - (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS));
     102
     103        for (;;)
     104                ;
     105        /* not reached */
     106}
     107
    94108/** @}
    95109 */

  • kernel/arch/sparc64/src/start.S

    re0b241f red166f7  
    6969        wrpr %g1, 0, %pstate
    7070
    71         wrpr %r0, 0, %pil               ! intialize %pil
     71        wrpr %g0, 0, %pil               ! intialize %pil
    7272
    7373        /*

  • kernel/arch/sparc64/src/trap/trap_table.S

    re0b241f red166f7  
    4141#include <arch/trap/exception.h>
    4242#include <arch/trap/mmu.h>
     43#include <arch/mm/mmu.h>
    4344#include <arch/mm/page.h>
    4445#include <arch/stack.h>
    … …  
    349350        wrpr %l0, %otherwin
    350351        wrpr %g0, %cansave
    351         wrpr %g0, NWINDOW-1, %cleanwin
     352        wrpr %g0, NWINDOW - 1, %cleanwin
    352353
    353354        /*
    … …  
    355356         */
    356357        mov VA_PRIMARY_CONTEXT_REG, %l0
    357         stxa %g0, [%l0] ASI_DMMU
    358         set kernel_image_start, %l0
    359         flush %l0
     358        stxa %g0, [%l0] ASI_DMMU
     359        rd %pc, %l0
     360        flush %l0
    360361
    361362        ba 1f
    … …  
    498499         */
    499500        wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
     501
     502        /*
     503         * Set primary context according to secondary context.
     504         */
     505        wr %g0, ASI_DMMU, %asi
     506        ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1
     507        stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi
     508        flush %o7
    500509       
    501510        rdpr %cwp, %g1
Note: See TracChangeset for help on using the changeset viewer.