Index: kernel/arch/sparc64/src/drivers/tick.c
===================================================================
--- kernel/arch/sparc64/src/drivers/tick.c	(revision b1c57a828cb73794beb6a309f5ec0199ca75ecc2)
+++ kernel/arch/sparc64/src/drivers/tick.c	(revision ec443d53cc8411f6b71e18809a8bf0563e29e90a)
@@ -35,4 +35,5 @@
 #include <arch/drivers/tick.h>
 #include <arch/interrupt.h>
+#include <arch/trap/interrupt.h>
 #include <arch/sparc64.h>
 #include <arch/asm.h>
@@ -51,5 +52,4 @@
 	softint_reg_t clear;
 
-	interrupt_register(14, "tick_int", tick_interrupt);
 	compare.int_dis = false;
 	compare.tick_cmpr = tick_counter_read() +
@@ -79,5 +79,5 @@
 /** Process tick interrupt.
  *
- * @param n      Interrupt Level (14, can be ignored)
+ * @param n      Trap type (0x4e, can be ignored)
  * @param istate Interrupted state.
  *
@@ -93,5 +93,5 @@
 	 * Make sure we are servicing interrupt_level_14
 	 */
-	ASSERT(n == 14);
+	ASSERT(n == TT_INTERRUPT_LEVEL_14);
 	
 	/*
Index: kernel/arch/sparc64/src/sun4u/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sun4u/sparc64.c	(revision b1c57a828cb73794beb6a309f5ec0199ca75ecc2)
+++ kernel/arch/sparc64/src/sun4u/sparc64.c	(revision ec443d53cc8411f6b71e18809a8bf0563e29e90a)
@@ -86,6 +86,8 @@
 void arch_pre_mm_init(void)
 {
-	if (config.cpu_active == 1)
+	if (config.cpu_active == 1) {
 		trap_init();
+		exc_arch_init();
+	}
 }
 
Index: kernel/arch/sparc64/src/trap/exception.c
===================================================================
--- kernel/arch/sparc64/src/trap/exception.c	(revision b1c57a828cb73794beb6a309f5ec0199ca75ecc2)
+++ kernel/arch/sparc64/src/trap/exception.c	(revision ec443d53cc8411f6b71e18809a8bf0563e29e90a)
@@ -55,5 +55,5 @@
 
 /** Handle instruction_access_exception. (0x8) */
-void instruction_access_exception(int n, istate_t *istate)
+void instruction_access_exception(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -62,5 +62,5 @@
 
 /** Handle instruction_access_error. (0xa) */
-void instruction_access_error(int n, istate_t *istate)
+void instruction_access_error(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -69,5 +69,5 @@
 
 /** Handle illegal_instruction. (0x10) */
-void illegal_instruction(int n, istate_t *istate)
+void illegal_instruction(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -76,5 +76,5 @@
 
 /** Handle privileged_opcode. (0x11) */
-void privileged_opcode(int n, istate_t *istate)
+void privileged_opcode(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -83,5 +83,5 @@
 
 /** Handle unimplemented_LDD. (0x12) */
-void unimplemented_LDD(int n, istate_t *istate)
+void unimplemented_LDD(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -90,5 +90,5 @@
 
 /** Handle unimplemented_STD. (0x13) */
-void unimplemented_STD(int n, istate_t *istate)
+void unimplemented_STD(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -97,5 +97,5 @@
 
 /** Handle fp_disabled. (0x20) */
-void fp_disabled(int n, istate_t *istate)
+void fp_disabled(unsigned int n, istate_t *istate)
 {
 	fprs_reg_t fprs;
@@ -117,5 +117,5 @@
 
 /** Handle fp_exception_ieee_754. (0x21) */
-void fp_exception_ieee_754(int n, istate_t *istate)
+void fp_exception_ieee_754(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -124,5 +124,5 @@
 
 /** Handle fp_exception_other. (0x22) */
-void fp_exception_other(int n, istate_t *istate)
+void fp_exception_other(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -131,5 +131,5 @@
 
 /** Handle tag_overflow. (0x23) */
-void tag_overflow(int n, istate_t *istate)
+void tag_overflow(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -138,5 +138,5 @@
 
 /** Handle division_by_zero. (0x28) */
-void division_by_zero(int n, istate_t *istate)
+void division_by_zero(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -145,5 +145,5 @@
 
 /** Handle data_access_exception. (0x30) */
-void data_access_exception(int n, istate_t *istate)
+void data_access_exception(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -152,5 +152,5 @@
 
 /** Handle data_access_error. (0x32) */
-void data_access_error(int n, istate_t *istate)
+void data_access_error(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -159,5 +159,5 @@
 
 /** Handle mem_address_not_aligned. (0x34) */
-void mem_address_not_aligned(int n, istate_t *istate)
+void mem_address_not_aligned(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -166,5 +166,5 @@
 
 /** Handle LDDF_mem_address_not_aligned. (0x35) */
-void LDDF_mem_address_not_aligned(int n, istate_t *istate)
+void LDDF_mem_address_not_aligned(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -173,5 +173,5 @@
 
 /** Handle STDF_mem_address_not_aligned. (0x36) */
-void STDF_mem_address_not_aligned(int n, istate_t *istate)
+void STDF_mem_address_not_aligned(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -180,5 +180,5 @@
 
 /** Handle privileged_action. (0x37) */
-void privileged_action(int n, istate_t *istate)
+void privileged_action(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -187,5 +187,5 @@
 
 /** Handle LDQF_mem_address_not_aligned. (0x38) */
-void LDQF_mem_address_not_aligned(int n, istate_t *istate)
+void LDQF_mem_address_not_aligned(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
@@ -194,5 +194,5 @@
 
 /** Handle STQF_mem_address_not_aligned. (0x39) */
-void STQF_mem_address_not_aligned(int n, istate_t *istate)
+void STQF_mem_address_not_aligned(unsigned int n, istate_t *istate)
 {
 	fault_if_from_uspace(istate, "%s.", __func__);
Index: kernel/arch/sparc64/src/trap/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/interrupt.c	(revision b1c57a828cb73794beb6a309f5ec0199ca75ecc2)
+++ kernel/arch/sparc64/src/trap/interrupt.c	(revision ec443d53cc8411f6b71e18809a8bf0563e29e90a)
@@ -36,4 +36,5 @@
 #include <arch/interrupt.h>
 #include <arch/trap/interrupt.h>
+#include <arch/trap/exception.h>
 #include <arch/sparc64.h>
 #include <interrupt.h>
@@ -43,4 +44,5 @@
 #include <arch/asm.h>
 #include <arch/barrier.h>
+#include <arch/drivers/tick.h>
 #include <print.h>
 #include <arch.h>
@@ -49,17 +51,74 @@
 #include <synch/spinlock.h>
 
-/** Register Interrupt Level Handler.
- *
- * @param n       Interrupt Level (1 - 15).
- * @param name    Short descriptive string.
- * @param handler Handler.
- *
- */
-void interrupt_register(unsigned int n, const char *name, iroutine_t handler)
+void exc_arch_init(void)
 {
-	ASSERT(n >= IVT_FIRST);
-	ASSERT(n <= IVT_ITEMS);
+	exc_register(TT_INSTRUCTION_ACCESS_EXCEPTION,
+	    "instruction_access_exception", false,
+	    instruction_access_exception);
+	exc_register(TT_INSTRUCTION_ACCESS_ERROR,
+	    "instruction_access_error", false,
+	    instruction_access_error);
+	exc_register(TT_ILLEGAL_INSTRUCTION,
+	    "illegal_instruction", false,
+	    illegal_instruction);
+	exc_register(TT_PRIVILEGED_OPCODE,
+	    "privileged_opcode", false,
+	    privileged_opcode);
+	exc_register(TT_UNIMPLEMENTED_LDD,
+	    "unimplemented_LDD", false,
+	    unimplemented_LDD);
+	exc_register(TT_UNIMPLEMENTED_STD,
+	    "unimplemented_STD", false,
+	    unimplemented_STD);
+	exc_register(TT_FP_DISABLED,
+	    "fp_disabled", true,
+	    fp_disabled);
+	exc_register(TT_FP_EXCEPTION_IEEE_754,
+	    "fp_exception_ieee_754", false,
+	    fp_exception_ieee_754);
+	exc_register(TT_FP_EXCEPTION_OTHER,
+	    "fp_exception_other", false,
+	    fp_exception_other);
+	exc_register(TT_TAG_OVERFLOW,
+	    "tag_overflow", false,
+	    tag_overflow);	
+	exc_register(TT_DIVISION_BY_ZERO,
+	    "division_by_zero", false,
+	    division_by_zero);
+	exc_register(TT_DATA_ACCESS_EXCEPTION,
+	    "data_access_exception", false,
+	    data_access_exception);
+	exc_register(TT_DATA_ACCESS_ERROR,
+	    "data_access_error", false,
+	    data_access_error);
+	exc_register(TT_MEM_ADDRESS_NOT_ALIGNED,
+	    "mem_address_not_aligned", false,
+	    mem_address_not_aligned);
+	exc_register(TT_LDDF_MEM_ADDRESS_NOT_ALIGNED,
+	    "LDDF_mem_address_not_aligned", false,
+	    LDDF_mem_address_not_aligned);
+	exc_register(TT_STDF_MEM_ADDRESS_NOT_ALIGNED,
+	    "STDF_mem_address_not_aligned", false,
+	    STDF_mem_address_not_aligned);
+	exc_register(TT_PRIVILEGED_ACTION,
+	    "privileged_action", false,
+	    privileged_action);
+	exc_register(TT_LDQF_MEM_ADDRESS_NOT_ALIGNED,
+	    "LDQF_mem_address_not_aligned", false,
+	    LDQF_mem_address_not_aligned);
+	exc_register(TT_STQF_MEM_ADDRESS_NOT_ALIGNED,
+	    "STQF_mem_address_not_aligned", false,
+	    STQF_mem_address_not_aligned);
+
+	exc_register(TT_INTERRUPT_LEVEL_14,
+	    "interrupt_level_14", true,
+	    tick_interrupt);
+
+#ifdef SUN4u 
+	exc_register(TT_INTERRUPT_VECTOR_TRAP,
+	    "interrupt_vector_trap", true,
+	    interrupt);
+#endif
 	
-	exc_register(n - IVT_FIRST, name, true, handler);
 }
 
Index: kernel/arch/sparc64/src/trap/sun4u/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/sun4u/interrupt.c	(revision b1c57a828cb73794beb6a309f5ec0199ca75ecc2)
+++ kernel/arch/sparc64/src/trap/sun4u/interrupt.c	(revision ec443d53cc8411f6b71e18809a8bf0563e29e90a)
@@ -53,5 +53,5 @@
  * @param istate Ignored.
  */
-void interrupt(int n, istate_t *istate)
+void interrupt(unsigned int n, istate_t *istate)
 {
 	uint64_t status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0);
Index: kernel/arch/sparc64/src/trap/sun4u/trap_table.S
===================================================================
--- kernel/arch/sparc64/src/trap/sun4u/trap_table.S	(revision b1c57a828cb73794beb6a309f5ec0199ca75ecc2)
+++ kernel/arch/sparc64/src/trap/sun4u/trap_table.S	(revision ec443d53cc8411f6b71e18809a8bf0563e29e90a)
@@ -63,5 +63,6 @@
 instruction_access_exception_tl0:
 	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x0a, TL = 0, instruction_access_error */
@@ -69,5 +70,6 @@
 .global instruction_access_error_tl0
 instruction_access_error_tl0:
-	PREEMPTIBLE_HANDLER instruction_access_error
+	mov TT_INSTRUCTION_ACCESS_ERROR, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x10, TL = 0, illegal_instruction */
@@ -75,5 +77,6 @@
 .global illegal_instruction_tl0
 illegal_instruction_tl0:
-	PREEMPTIBLE_HANDLER illegal_instruction
+	mov TT_ILLEGAL_INSTRUCTION, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x11, TL = 0, privileged_opcode */
@@ -81,5 +84,6 @@
 .global privileged_opcode_tl0
 privileged_opcode_tl0:
-	PREEMPTIBLE_HANDLER privileged_opcode
+	mov TT_PRIVILEGED_OPCODE, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x12, TL = 0, unimplemented_LDD */
@@ -87,5 +91,6 @@
 .global unimplemented_LDD_tl0
 unimplemented_LDD_tl0:
-	PREEMPTIBLE_HANDLER unimplemented_LDD
+	mov TT_UNIMPLEMENTED_LDD, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x13, TL = 0, unimplemented_STD */
@@ -93,5 +98,6 @@
 .global unimplemented_STD_tl0
 unimplemented_STD_tl0:
-	PREEMPTIBLE_HANDLER unimplemented_STD
+	mov TT_UNIMPLEMENTED_STD, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x20, TL = 0, fb_disabled handler */
@@ -99,5 +105,6 @@
 .global fb_disabled_tl0
 fp_disabled_tl0:
-	PREEMPTIBLE_HANDLER fp_disabled
+	mov TT_FP_DISABLED, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
@@ -105,5 +112,6 @@
 .global fb_exception_ieee_754_tl0
 fp_exception_ieee_754_tl0:
-	PREEMPTIBLE_HANDLER fp_exception_ieee_754
+	mov TT_FP_EXCEPTION_IEEE_754, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x22, TL = 0, fb_exception_other handler */
@@ -111,5 +119,6 @@
 .global fb_exception_other_tl0
 fp_exception_other_tl0:
-	PREEMPTIBLE_HANDLER fp_exception_other
+	mov TT_FP_EXCEPTION_OTHER, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x23, TL = 0, tag_overflow */
@@ -117,5 +126,6 @@
 .global tag_overflow_tl0
 tag_overflow_tl0:
-	PREEMPTIBLE_HANDLER tag_overflow
+	mov TT_TAG_OVERFLOW, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x24, TL = 0, clean_window handler */
@@ -129,5 +139,6 @@
 .global division_by_zero_tl0
 division_by_zero_tl0:
-	PREEMPTIBLE_HANDLER division_by_zero
+	mov TT_DIVISION_BY_ZERO, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x30, TL = 0, data_access_exception */
@@ -136,5 +147,6 @@
 data_access_exception_tl0:
 	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DATA_ACCESS_EXCEPTION, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x32, TL = 0, data_access_error */
@@ -142,5 +154,6 @@
 .global data_access_error_tl0
 data_access_error_tl0:
-	PREEMPTIBLE_HANDLER data_access_error
+	mov TT_DATA_ACCESS_ERROR, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x34, TL = 0, mem_address_not_aligned */
@@ -148,5 +161,6 @@
 .global mem_address_not_aligned_tl0
 mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER mem_address_not_aligned
+	mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
@@ -154,5 +168,6 @@
 .global LDDF_mem_address_not_aligned_tl0
 LDDF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER LDDF_mem_address_not_aligned
+	mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
@@ -160,5 +175,6 @@
 .global STDF_mem_address_not_aligned_tl0
 STDF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER STDF_mem_address_not_aligned
+	mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x37, TL = 0, privileged_action */
@@ -166,5 +182,6 @@
 .global privileged_action_tl0
 privileged_action_tl0:
-	PREEMPTIBLE_HANDLER privileged_action
+	mov TT_PRIVILEGED_ACTION, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
@@ -172,5 +189,6 @@
 .global LDQF_mem_address_not_aligned_tl0
 LDQF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER LDQF_mem_address_not_aligned
+	mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
@@ -178,5 +196,6 @@
 .global STQF_mem_address_not_aligned_tl0
 STQF_mem_address_not_aligned_tl0:
-	PREEMPTIBLE_HANDLER STQF_mem_address_not_aligned
+	mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x41, TL = 0, interrupt_level_1 handler */
@@ -184,5 +203,6 @@
 .global interrupt_level_1_handler_tl0
 interrupt_level_1_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 1
+	mov TT_INTERRUPT_LEVEL_1, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x42, TL = 0, interrupt_level_2 handler */
@@ -190,5 +210,6 @@
 .global interrupt_level_2_handler_tl0
 interrupt_level_2_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 2
+	mov TT_INTERRUPT_LEVEL_2, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x43, TL = 0, interrupt_level_3 handler */
@@ -196,5 +217,6 @@
 .global interrupt_level_3_handler_tl0
 interrupt_level_3_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 3
+	mov TT_INTERRUPT_LEVEL_3, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x44, TL = 0, interrupt_level_4 handler */
@@ -202,5 +224,6 @@
 .global interrupt_level_4_handler_tl0
 interrupt_level_4_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 4
+	mov TT_INTERRUPT_LEVEL_4, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x45, TL = 0, interrupt_level_5 handler */
@@ -208,5 +231,6 @@
 .global interrupt_level_5_handler_tl0
 interrupt_level_5_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 5
+	mov TT_INTERRUPT_LEVEL_5, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x46, TL = 0, interrupt_level_6 handler */
@@ -214,5 +238,6 @@
 .global interrupt_level_6_handler_tl0
 interrupt_level_6_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 6
+	mov TT_INTERRUPT_LEVEL_6, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x47, TL = 0, interrupt_level_7 handler */
@@ -220,5 +245,6 @@
 .global interrupt_level_7_handler_tl0
 interrupt_level_7_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 7
+	mov TT_INTERRUPT_LEVEL_7, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x48, TL = 0, interrupt_level_8 handler */
@@ -226,5 +252,6 @@
 .global interrupt_level_8_handler_tl0
 interrupt_level_8_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 8
+	mov TT_INTERRUPT_LEVEL_8, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x49, TL = 0, interrupt_level_9 handler */
@@ -232,5 +259,6 @@
 .global interrupt_level_9_handler_tl0
 interrupt_level_9_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 9
+	mov TT_INTERRUPT_LEVEL_9, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4a, TL = 0, interrupt_level_10 handler */
@@ -238,5 +266,6 @@
 .global interrupt_level_10_handler_tl0
 interrupt_level_10_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 10
+	mov TT_INTERRUPT_LEVEL_10, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4b, TL = 0, interrupt_level_11 handler */
@@ -244,5 +273,6 @@
 .global interrupt_level_11_handler_tl0
 interrupt_level_11_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 11
+	mov TT_INTERRUPT_LEVEL_11, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4c, TL = 0, interrupt_level_12 handler */
@@ -250,5 +280,6 @@
 .global interrupt_level_12_handler_tl0
 interrupt_level_12_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 12
+	mov TT_INTERRUPT_LEVEL_12, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4d, TL = 0, interrupt_level_13 handler */
@@ -256,5 +287,6 @@
 .global interrupt_level_13_handler_tl0
 interrupt_level_13_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 13
+	mov TT_INTERRUPT_LEVEL_13, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4e, TL = 0, interrupt_level_14 handler */
@@ -262,5 +294,6 @@
 .global interrupt_level_14_handler_tl0
 interrupt_level_14_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 14
+	mov TT_INTERRUPT_LEVEL_14, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x4f, TL = 0, interrupt_level_15 handler */
@@ -268,5 +301,6 @@
 .global interrupt_level_15_handler_tl0
 interrupt_level_15_handler_tl0:
-	INTERRUPT_LEVEL_N_HANDLER 15
+	mov TT_INTERRUPT_LEVEL_15, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x60, TL = 0, interrupt_vector_trap handler */
@@ -274,5 +308,6 @@
 .global interrupt_vector_trap_handler_tl0
 interrupt_vector_trap_handler_tl0:
-	INTERRUPT_VECTOR_TRAP_HANDLER
+	mov TT_INTERRUPT_VECTOR_TRAP, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
@@ -356,5 +391,6 @@
 	wrpr %g0, 1, %tl
 	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
-	PREEMPTIBLE_HANDLER instruction_access_exception
+	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch 
 
 /* TT = 0x0a, TL > 0, instruction_access_error */
@@ -363,5 +399,6 @@
 instruction_access_error_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER instruction_access_error
+	mov TT_INSTRUCTION_ACCESS_ERROR, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x10, TL > 0, illegal_instruction */
@@ -370,5 +407,6 @@
 illegal_instruction_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER illegal_instruction
+	mov TT_ILLEGAL_INSTRUCTION, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x24, TL > 0, clean_window handler */
@@ -383,5 +421,6 @@
 division_by_zero_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER division_by_zero
+	mov TT_DIVISION_BY_ZERO, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x30, TL > 0, data_access_exception */
@@ -391,5 +430,6 @@
 	wrpr %g0, 1, %tl
 	wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate
-	PREEMPTIBLE_HANDLER data_access_exception
+	mov TT_DATA_ACCESS_EXCEPTION, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x32, TL > 0, data_access_error */
@@ -398,5 +438,6 @@
 data_access_error_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER data_access_error
+	mov TT_DATA_ACCESS_ERROR, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x34, TL > 0, mem_address_not_aligned */
@@ -405,5 +446,6 @@
 mem_address_not_aligned_tl1:
 	wrpr %g0, 1, %tl
-	PREEMPTIBLE_HANDLER mem_address_not_aligned
+	mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
