Changeset eadaeae8 in mainline for uspace/drv/bus/usb
- Timestamp:
- 2018-03-21T20:58:49Z (8 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3be9d10
- Parents:
- 874381a
- Location:
- uspace/drv/bus/usb
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/ohci/hc.c
r874381a readaeae8 512 512 513 513 /* Enable interrupts */ 514 if ( instance->base.irq_cap >= 0) {514 if (CAP_HANDLE_VALID(instance->base.irq_handle)) { 515 515 OHCI_WR(instance->registers->interrupt_enable, 516 516 OHCI_USED_INTERRUPTS); -
uspace/drv/bus/usb/uhci/hc.c
r874381a readaeae8 294 294 pio_write_32(®isters->flbaseadd, pa); 295 295 296 if ( instance->base.irq_cap >= 0) {296 if (CAP_HANDLE_VALID(instance->base.irq_handle)) { 297 297 /* Enable all interrupts, but resume interrupt */ 298 298 pio_write_16(&instance->registers->usbintr, -
uspace/drv/bus/usb/xhci/hc.c
r874381a readaeae8 495 495 XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA, erstba_phys); 496 496 497 if ( hc->base.irq_cap > 0) {497 if (CAP_HANDLE_VALID(hc->base.irq_handle)) { 498 498 XHCI_REG_SET(intr0, XHCI_INTR_IE, 1); 499 499 XHCI_REG_SET(hc->op_regs, XHCI_OP_INTE, 1);
Note:
See TracChangeset
for help on using the changeset viewer.