Changeset e7b7be3f in mainline for kernel/arch/sparc64/include

Timestamp:

2007-01-22T13:10:08Z (19 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0f3fc9b

Parents:

62c63fc

Message:

asm volatile → asm volatile

Location:

kernel/arch/sparc64/include

Files:

• asm.h (modified) (23 diffs)
• atomic.h (modified) (3 diffs)
• barrier.h (modified) (4 diffs)

kernel/arch/sparc64/include/asm.h

@@ -52 +52 @@
         uint64_t v;
         
-        __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
+        asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
         
         return v;
@@ -63 +63 @@
 static inline void pstate_write(uint64_t v)
 {
-        __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
+        asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
 }
 
@@ -74 +74 @@
         uint64_t v;
         
-        __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
+        asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
         
         return v;
@@ -85 +85 @@
 static inline void tick_compare_write(uint64_t v)
 {
-        __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
+        asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
 }
 
@@ -96 +96 @@
         uint64_t v;
         
-        __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
+        asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
         
         return v;
@@ -107 +107 @@
 static inline void tick_write(uint64_t v)
 {
-        __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
+        asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
 }
 
@@ -118 +118 @@
         uint64_t v;
         
-        __asm__ volatile ("rd %%fprs, %0\n" : "=r" (v));
+        asm volatile ("rd %%fprs, %0\n" : "=r" (v));
         
         return v;
@@ -129 +129 @@
 static inline void fprs_write(uint64_t v)
 {
-        __asm__ volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
+        asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
 }
 
@@ -140 +140 @@
         uint64_t v;
 
-        __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
+        asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
         return v;
@@ -151 +151 @@
 static inline void softint_write(uint64_t v)
 {
-        __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
+        asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
 }
 
@@ -162 +162 @@
 static inline void clear_softint_write(uint64_t v)
 {
-        __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
+        asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
 }
 
@@ -173 +173 @@
 static inline void set_softint_write(uint64_t v)
 {
-        __asm__ volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
+        asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
 }
 
@@ -248 +248 @@
         uintptr_t unbiased_sp;
         
-        __asm__ volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
+        asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
         
         return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
@@ -261 +261 @@
         uint64_t v;
         
-        __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
+        asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
         
         return v;
@@ -274 +274 @@
         uint64_t v;
         
-        __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
+        asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
         
         return v;
@@ -287 +287 @@
         uint64_t v;
         
-        __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
+        asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
         
         return v;
@@ -300 +300 @@
         uint64_t v;
         
-        __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
+        asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
         
         return v;
@@ -311 +311 @@
 static inline void tba_write(uint64_t v)
 {
-        __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
+        asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
 }
 
@@ -325 +325 @@
         uint64_t v;
         
-        __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
+        asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
         
         return v;
@@ -338 +338 @@
 static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
 {
-        __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
+        asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
 }
 
@@ -344 +344 @@
 static inline void flushw(void)
 {
-        __asm__ volatile ("flushw\n");
+        asm volatile ("flushw\n");
 }
 
@@ -350 +350 @@
 static inline void nucleus_enter(void)
 {
-        __asm__ volatile ("wrpr %g0, 1, %tl\n");
+        asm volatile ("wrpr %g0, 1, %tl\n");
 }
 
@@ -356 +356 @@
 static inline void nucleus_leave(void)
 {
-        __asm__ volatile ("wrpr %g0, %g0, %tl\n");
+        asm volatile ("wrpr %g0, %g0, %tl\n");
 }
 

kernel/arch/sparc64/include/atomic.h

@@ -58 +58 @@
                 a = *((uint64_t *) x);
                 b = a + i;
-                __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a));
+                asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a));
         } while (a != b);
 
@@ -99 +99 @@
         volatile uintptr_t x = (uint64_t) &val->count;
 
-        __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0));
+        asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0));
 
         return v;
@@ -111 +111 @@
         volatile uintptr_t x = (uint64_t) &val->count;
 
-        __asm__ volatile (
+        asm volatile (
         "0:\n"
                 "casx %0, %3, %1\n"

kernel/arch/sparc64/include/barrier.h

@@ -40 +40 @@
  */
 #define CS_ENTER_BARRIER()                              \
-        __asm__ volatile (                              \
+        asm volatile (                          \
                 "membar #LoadLoad | #LoadStore\n"       \
                 ::: "memory"                            \
         )
 #define CS_LEAVE_BARRIER()                              \
-        __asm__ volatile (                              \
+        asm volatile (                          \
                 "membar #StoreStore\n"                  \
                 "membar #LoadStore\n"                   \
@@ -52 +52 @@
 
 #define memory_barrier()        \
-        __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
+        asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
 #define read_barrier()          \
-        __asm__ volatile ("membar #LoadLoad\n" ::: "memory")
+        asm volatile ("membar #LoadLoad\n" ::: "memory")
 #define write_barrier()         \
-        __asm__ volatile ("membar #StoreStore\n" ::: "memory")
+        asm volatile ("membar #StoreStore\n" ::: "memory")
 
 /** Flush Instruction Memory instruction. */
@@ -71 +71 @@
          */
          
-        __asm__ volatile ("flush %o7\n");
+        asm volatile ("flush %o7\n");
 }
 
@@ -77 +77 @@
 static inline void membar(void)
 {
-        __asm__ volatile ("membar #Sync\n");
+        asm volatile ("membar #Sync\n");
 }