Changeset e3f41b6 in mainline for arch

Timestamp:

2005-06-06T20:01:57Z (21 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b0bf501

Parents:

d47f0e1

Message:

Code cleanup in scheduler.c thread.c - removed unnecessary spinlock.
atomic_inc, atomic_dec moved to arch/atomic.h instead of arch/smp/atomic.h,
advisable to use even in non-smp mode.
Fixed atomic_inc, atomic_dec in mips architecture.

Location:

arch

Files:

• ia32/Makefile.inc (modified) (1 diff)
• ia32/include/atomic.h (moved) (moved from arch/ia32/include/smp/atomic.h ) (1 diff)
• ia32/src/atomic.S (moved) (moved from arch/ia32/src/smp/atomic.S ) (2 diffs)
• mips/_link.ld (modified) (1 diff)
• mips/include/atomic.h (moved) (moved from arch/mips/include/smp/atomic.h ) (1 diff)

arch/ia32/Makefile.inc

@@ -31 +31 @@
         arch/smp/mps.c \
         arch/smp/smp.c \
-        arch/smp/atomic.S \
+        arch/atomic.S \
         arch/smp/ipi.c \
         arch/ia32.c \

arch/ia32/include/atomic.h

@@ -32 +32 @@
 #include <arch/types.h>
 
-extern void atomic_inc(int *val);
-extern void atomic_dec(int *val);
+extern void atomic_inc(volatile int *val);
+extern void atomic_dec(volatile int *val);
 
 extern int test_and_set(int *val);

arch/ia32/src/atomic.S

@@ -33 +33 @@
         pushl %ebx
         movl 8(%esp),%ebx
+#ifdef __SMP__  
         lock incl (%ebx)
+#else
+        incl (%ebx)
+#endif          
         popl %ebx
         ret
@@ -41 +45 @@
         pushl %ebx
         movl 8(%esp),%ebx
+#ifdef __SMP__  
         lock decl (%ebx)
+#else
+        decl (%ebx)
+#endif
         popl %ebx
         ret

arch/mips/_link.ld

@@ -8 +8 @@
 
 OUTPUT_FORMAT(binary)
-ENTRY(kernel_image_start)
+ENTRY(kernel_image_start) 
 
 SECTIONS {

arch/mips/include/atomic.h

@@ -30 +30 @@
 #define __MIPS_ATOMIC_H__
 
-#define atomic_inc(x)   ((*x)++)
-#define atomic_dec(x)   ((*x)--)
+#define atomic_inc(x)   (a_add(x,1))
+#define atomic_dec(x)   (a_sub(x,1))
+
+/*
+ * Atomic addition
+ *
+ * This case is harder, and we have to use the special LL and SC operations
+ * to achieve atomicity. The instructions are similar to LW (load) and SW
+ * (store), except that the LL (load-linked) instruction loads the address
+ * of the variable to a special register and if another process writes to
+ * the same location, the SC (store-conditional) instruction fails.
+ */
+static inline int a_add( volatile int *val, int i)
+{
+        int tmp, tmp2;
+
+        asm volatile (
+                "       .set    push\n"
+                "       .set    noreorder\n"
+                "       nop\n"
+                "1:\n"
+                "       ll      %0, %1\n"
+                "       addu    %0, %0, %2\n"
+                "       move    %3, %0\n"
+                "       sc      %0, %1\n"
+                "       beq     %0, 0x0, 1b\n"
+                "       move    %0, %3\n"
+                "       .set    pop\n"
+                : "=&r" (tmp), "=o" (*val)
+                : "r" (i), "r" (tmp2)
+                );
+        return tmp;
+}
+
+
+/*
+ * Atomic subtraction
+ *
+ * Implemented in the same manner as a_add, except we substract the value.
+ */
+static inline int a_sub( volatile int *val, int i)
+
+{
+        int tmp, tmp2;
+
+        asm volatile (
+                "       .set    push\n"
+                "       .set    noreorder\n"
+                "       nop\n"
+                "1:\n"
+                "       ll      %0, %1\n"
+                "       subu    %0, %0, %2\n"
+                "       move    %3, %0\n"
+                "       sc      %0, %1\n"
+                "       beq     %0, 0x0, 1b\n"
+                "       move    %0, %3\n"
+                "       .set    pop\n"
+                : "=&r" (tmp), "=o" (*val)
+                : "r" (i), "r" (tmp2)
+                );
+        return tmp;
+}
+
 
 #endif