Index: arch/amd64/src/asm_utils.S
===================================================================
--- arch/amd64/src/asm_utils.S	(revision e3b9572bf65a7338c20a539433408504a314d0dd)
+++ arch/amd64/src/asm_utils.S	(revision e3b9572bf65a7338c20a539433408504a314d0dd)
@@ -0,0 +1,144 @@
+#
+# Copyright (C) 2005 Ondrej Palkovsky
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+# - The name of the author may not be used to endorse or promote products
+#   derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+
+#  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
+# and 1 means interrupt with error word
+
+	
+#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
+
+#define __ASM__
+#include <arch/pm.h>
+	
+.text
+.global interrupt_handlers
+.global panic_printf
+
+panic_printf:
+	movq $halt, (%rsp)
+	jmp printf
+
+# Push all general purpose registers on stack except %rbp, %rsp
+.macro push_all_gpr
+	pushq %rax 
+	pushq %rbx
+	pushq %rcx
+	pushq %rdx
+	pushq %rsi
+	pushq %rdi
+	pushq %r8
+	pushq %r9
+	pushq %r10
+	pushq %r11
+	pushq %r12
+	pushq %r13
+	pushq %r14
+	pushq %r15
+.endm
+
+.macro pop_all_gpr
+	popq %r15
+	popq %r14
+	popq %r13
+	popq %r12
+	popq %r11
+	popq %r10
+	popq %r9
+	popq %r8
+	popq %rdi
+	popq %rsi
+	popq %rdx
+	popq %rcx
+	popq %rbx
+	popq %rax
+.endm
+	
+## Declare interrupt handlers
+#
+# Declare interrupt handlers for n interrupt
+# vectors starting at vector i.
+#
+# The handlers setup data segment registers
+# and call trap_dispatcher().
+#
+.macro handler i n
+	pushq %rbp
+	movq %rsp,%rbp
+	
+	push_all_gpr
+
+	# trap_dispatcher(i, stack)
+	movq $(\i),%rdi   # %rdi - first parameter
+	movq %rbp, %rsi
+	addq $8, %rsi     # %rsi - second parameter - original stack
+	call trap_dispatcher
+
+# Test if this is interrupt with error word or not
+	mov $\i,%cl;
+	movl $1,%eax;
+	test $0xe0,%cl;
+	jnz 0f;
+	and $0x1f,%cl;
+	shl %cl,%eax;
+	and $ERROR_WORD_INTERRUPT_LIST,%eax;
+	jz 0f;
+
+
+# Return with error word
+	pop_all_gpr
+	
+	popq %rbp;
+	add $8,%esp;    # Skip error word
+	iretq
+
+0:
+# Return with no error word
+	pop_all_gpr
+	
+	popq %rbp
+	iretq
+
+	.if (\n-\i)-1
+	handler "(\i+1)",\n
+	.endif
+.endm
+	
+interrupt_handlers:
+h_start:
+	handler 0 IDT_ITEMS
+#	handler 64 128	
+#	handler 128 192
+#	handler 192 256
+h_end:
+	
+	
+.data
+.global interrupt_handler_size
+
+interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
Index: arch/amd64/src/boot/memmap.S
===================================================================
--- arch/amd64/src/boot/memmap.S	(revision d9f81af379b969bda6be5f57bbcb8db7400c521c)
+++ arch/amd64/src/boot/memmap.S	(revision e3b9572bf65a7338c20a539433408504a314d0dd)
@@ -117,5 +117,5 @@
 	#memory size in 1 kb chunks
 e801memorysize:
-	.long	0
+	.long 0x0
 
 e820counter:
Index: arch/amd64/src/dummy.s
===================================================================
--- arch/amd64/src/dummy.s	(revision d9f81af379b969bda6be5f57bbcb8db7400c521c)
+++ arch/amd64/src/dummy.s	(revision e3b9572bf65a7338c20a539433408504a314d0dd)
@@ -31,5 +31,4 @@
 .global userspace
 .global before_thread_runs_arch
-.global panic_printf
 .global cpu_identify
 .global cpu_arch_init
@@ -38,5 +37,4 @@
 .global arch_late_init
 .global calibrate_delay_loop
-.global cpu_halt
 .global dummy
 .global rdtsc
@@ -44,6 +42,4 @@
 .global fpu_init
 	
-.global interrupt_handler_size
-.global interrupt_handlers
 .global memory_print_map
 .global get_memory_size
@@ -53,11 +49,8 @@
 	ret
 
-interrupt_handler_size:
-interrupt_handlers:	
 rdtsc:
 before_thread_runs_arch:
 userspace:
 calibrate_delay_loop:
-panic_printf:
 cpu_identify:
 cpu_arch_init:
@@ -66,5 +59,4 @@
 arch_late_init:
 calibrate_delay_loop:
-cpu_halt:
 reset_TS_flag:
 fpu_init:
Index: arch/amd64/src/pm.c
===================================================================
--- arch/amd64/src/pm.c	(revision d9f81af379b969bda6be5f57bbcb8db7400c521c)
+++ arch/amd64/src/pm.c	(revision e3b9572bf65a7338c20a539433408504a314d0dd)
@@ -181,5 +181,5 @@
 	trap_register(13, gp_fault);
 	trap_register( 7, nm_fault);
-	trap_register(12, ss_fault);
+	trap_register(12, ss_fault);	
 }
 
