Changeset e1be3b6 in mainline for arch/amd64/src
- Timestamp:
- 2006-03-23T21:18:58Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9cbd27b
- Parents:
- 3b712407
- Location:
- arch/amd64/src
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/amd64/src/amd64.c
r3b712407 re1be3b6 164 164 } 165 165 166 /** Set Thread-local-storeage pointer166 /** Set thread-local-storage pointer 167 167 * 168 168 * TLS pointer is set in FS register. Unfortunately the 64-bit 169 169 * part can be set only in CPL0 mode. 170 170 * 171 * The specs say s, that on %fs:0 there is stored contents of %fs register,171 * The specs say, that on %fs:0 there is stored contents of %fs register, 172 172 * we need not to go to CPL0 to read it. 173 173 */ -
arch/amd64/src/asm_utils.S
r3b712407 re1be3b6 181 181 * a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp 182 182 * can result in two instructions with different op-code lengths. 183 * Therefore, pay special attention to the extra NOP's that serve as 184 * a necessary fill. 183 * Therefore we align the interrupt handlers. 185 184 */ 186 185
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