Changeset e11ae91 in mainline for kernel/arch/sparc64/src

Timestamp:

2006-08-30T11:31:25Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ee454eb

Parents:

0fa6044

Message:

sparc64 work.

• Modify before_thread_runs_arch() to store addresses of the kernel stack and

userspace window buffer, resp., to registers %g6 and %g7, resp, in the
alternate and interrupt global sets.

• Modify after_thread_ran_arch() to sample %g7 from the alternate globals.
• Implement trap handler for spilling register windows into userspace window buffer.
• Implement assembly language functions to access %g6 and %g7 registers in the alternate sets.
• Initialize the trap table so that there are now also spill_1_normal, spill_2_normal,

spill_0_other and fill_1_normal handlers. These handlers are used in different situations
and for different purposes.

Location:

kernel/arch/sparc64/src

Files:

• asm.S (modified) (1 diff)
• proc/scheduler.c (modified) (4 diffs)
• trap/trap_table.S (modified) (4 diffs)

kernel/arch/sparc64/src/asm.S

@@ -107 +107 @@
         b _memsetb
         nop
+
+
+.macro WRITE_ALTERNATE_REGISTER reg, bit
+        save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
+        rdpr %pstate, %l0
+        wrpr %l0, \bit, %pstate
+        mov %i0, \reg
+        wrpr %l0, 0, %pstate
+        ret
+        restore
+.endm
+
+.macro READ_ALTERNATE_REGISTER reg, bit
+        save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
+        rdpr %pstate, %l0
+        wrpr %l0, \bit, %pstate
+        mov \reg, %i0
+        wrpr %l0, 0, %pstate
+        ret
+        restore
+.endm
+
+.global write_to_ag_g6
+write_to_ag_g6:
+        WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT
+
+.global write_to_ag_g7
+write_to_ag_g7:
+        WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
+
+.global write_to_ig_g6
+write_to_ig_g6:
+        WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT
+
+.global read_from_ag_g7
+read_from_ag_g7:
+        READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT

kernel/arch/sparc64/src/proc/scheduler.c

@@ -37 +37 @@
 #include <arch.h>
 #include <arch/asm.h>
+#include <arch/regdef.h>
+#include <arch/stack.h>
 #include <arch/mm/tlb.h>
 #include <arch/mm/page.h>
@@ -52 +54 @@
  * Ensure that thread's kernel stack, as well as userspace window
  * buffer for userspace threads, are locked in DTLB.
+ * For userspace threads, initialize reserved global registers
+ * in the alternate and interrupt sets.
  */
 void before_thread_runs_arch(void)
@@ -83 +87 @@
                         dtlb_insert_mapping(uw_buf, KA2PA(uw_buf), PAGESIZE_8K, true, true);
                 }
+                
+                /*
+                 * Write kernel stack address to %g6 and a pointer to the last item
+                 * in the userspace window buffer to %g7 in the alternate and interrupt sets.
+                 */
+                write_to_ig_g6((uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS);
+                write_to_ag_g6((uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS);
+                write_to_ag_g7((uintptr_t) THREAD->arch.uspace_window_buffer);
         }
 }
@@ -124 +136 @@
                         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, (uintptr_t) uw_buf);
                 }
+        
+                /* sample the state of the userspace window buffer */   
+                THREAD->arch.uspace_window_buffer = (uint8_t *) read_from_ag_g7();
         }
 }

kernel/arch/sparc64/src/trap/trap_table.S

@@ -204 +204 @@
         SPILL_NORMAL_HANDLER_KERNEL
 
+/* TT = 0x84, TL = 0, spill_1_normal handler */
+.org trap_table + TT_SPILL_1_NORMAL*ENTRY_SIZE
+.global spill_1_normal
+spill_1_normal:
+        SPILL_NORMAL_HANDLER_USERSPACE
+
+/* TT = 0x88, TL = 0, spill_2_normal handler */
+.org trap_table + TT_SPILL_2_NORMAL*ENTRY_SIZE
+.global spill_2_normal
+spill_2_normal:
+        SPILL_TO_USPACE_WINDOW_BUFFER
+
 /* TT = 0xc0, TL = 0, fill_0_normal handler */
 .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
@@ -210 +222 @@
         FILL_NORMAL_HANDLER_KERNEL
 
+/* TT = 0xc4, TL = 0, fill_1_normal handler */
+.org trap_table + TT_FILL_1_NORMAL*ENTRY_SIZE
+.global fill_1_normal
+fill_1_normal:
+        FILL_NORMAL_HANDLER_USERSPACE
+
 /*
  * Handlers for TL>0.
@@ -267 +285 @@
 spill_0_normal_high:
         SPILL_NORMAL_HANDLER_KERNEL
+
+/* TT = 0x88, TL > 0, spill_2_normal handler */
+.org trap_table + (TT_SPILL_2_NORMAL+512)*ENTRY_SIZE
+.global spill_2_normal_high
+spill_2_normal_high:
+        SPILL_TO_USPACE_WINDOW_BUFFER
+
+/* TT = 0xa0, TL > 0, spill_0_other handler */
+.org trap_table + (TT_SPILL_0_OTHER+512)*ENTRY_SIZE
+.global spill_0_other_high
+spill_0_other_high:
+        SPILL_TO_USPACE_WINDOW_BUFFER
 
 /* TT = 0xc0, TL > 0, fill_0_normal handler */
@@ -290 +320 @@
  *      %g2             Argument for the function.
  *      %g6             Pre-set as kernel stack base if trap from userspace.
- *      %g7             Reserved.
+ *      %g7             Pre-set as address of the userspace window buffer.
  */
 .global preemptible_handler