Index: uspace/lib/drv/include/pci_dev_iface.h
===================================================================
--- uspace/lib/drv/include/pci_dev_iface.h	(revision 6413967015f267b604e85eb4c9a5f071af52a1b0)
+++ uspace/lib/drv/include/pci_dev_iface.h	(revision e07257ea61be24fb24dc38d84ded801cd8c1af5d)
@@ -42,6 +42,16 @@
 #define PCI_VENDOR_ID	0x00
 #define PCI_DEVICE_ID	0x02
+#define PCI_STATUS 	0x06
 #define PCI_SUB_CLASS	0x0A
 #define PCI_BASE_CLASS	0x0B
+#define PCI_CAP_PTR	0x34
+
+#define PCI_STATUS_CAP_LIST	(1 << 4)
+
+#define PCI_CAP_ID(c)	((c) + 0x0)
+#define PCI_CAP_NEXT(c)	((c) + 0x1)
+
+#define PCI_CAP_PMID		0x1
+#define PCI_CAP_VENDORSPECID	0x9
 
 extern errno_t pci_config_space_read_8(async_sess_t *, uint32_t, uint8_t *);
@@ -52,4 +62,38 @@
 extern errno_t pci_config_space_write_16(async_sess_t *, uint32_t, uint16_t);
 extern errno_t pci_config_space_write_32(async_sess_t *, uint32_t, uint32_t);
+
+static inline errno_t
+pci_config_space_cap_first(async_sess_t *sess, uint8_t *c, uint8_t *id)
+{
+	errno_t rc;
+	uint16_t status;
+
+	rc = pci_config_space_read_16(sess, PCI_STATUS, &status);
+	if (rc != EOK)
+		return rc;
+
+	if (!(status & PCI_STATUS_CAP_LIST)) {
+		*c = 0;
+		return EOK;
+	}
+
+	rc = pci_config_space_read_8(sess, PCI_CAP_PTR, c);
+	if (rc != EOK)
+		return rc;
+	if (!c)
+		return EOK;
+	return pci_config_space_read_8(sess, PCI_CAP_ID(*c), id);
+}
+
+static inline errno_t
+pci_config_space_cap_next(async_sess_t *sess, uint8_t *c, uint8_t *id)
+{
+	errno_t rc = pci_config_space_read_8(sess, PCI_CAP_NEXT(*c), c);
+	if (rc != EOK)
+		return rc;
+	if (!c)
+		return EOK;
+	return pci_config_space_read_8(sess, PCI_CAP_ID(*c), id);
+}
 
 /** PCI device communication interface. */