Changeset df7f5cea in mainline for kernel/arch/ppc32/src

Timestamp:

2014-08-25T23:03:50Z (11 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

1c635d6, 3ab2d1e

Parents:

6dbe7f68

Message:

Experimental support for hard-floats on ppc32.

• By default disabled.

Location:

kernel/arch/ppc32/src

Files:

• cpu/cpu.c (modified) (2 diffs)
• exception.S (modified) (2 diffs)
• fpu_context.S (modified) (4 diffs)
• interrupt.c (modified) (3 diffs)

kernel/arch/ppc32/src/cpu/cpu.c

@@ -37 +37 @@
 #include <arch.h>
 #include <print.h>
+#include <fpu_context.h>
 
 void cpu_arch_init(void)
 {
+#ifdef CONFIG_FPU
+        fpu_enable();
+#endif
 }
 
@@ -52 +56 @@
         
         switch (cpu->arch.version) {
-                case 8:
-                        name = "PowerPC 750";
-                        break;
-                case 9:
-                        name = "PowerPC 604e";
-                        break;
-                case 0x81:
-                        name = "PowerPC 8260";
-                        break;
-                case 0x8081:
-                        name = "PowerPC 826xA";
-                        break;
-                default:
-                        name = "unknown";
+        case 8:
+                name = "PowerPC 750";
+                break;
+        case 9:
+                name = "PowerPC 604e";
+                break;
+        case 0x81:
+                name = "PowerPC 8260";
+                break;
+        case 0x8081:
+                name = "PowerPC 826xA";
+                break;
+        default:
+                name = "unknown";
         }
         

kernel/arch/ppc32/src/exception.S

@@ -258 +258 @@
         mtsrr0 r12
         
+        mfsrr1 r5
+        andi. r5, r5, MSR_FP
         mfmsr r12
+        or r12, r12, r5         # Propagate MSR_FP from SRR1 to MSR
         ori r12, r12, (MSR_IR | MSR_DR)@l
         mtsrr1 r12
@@ -276 +279 @@
         addi r12, r12, iret_syscall@l
         mtlr r12
-        
+
+        mfsrr1 r0
+        andi. r0, r0, MSR_FP
         mfmsr r12
+        or r12, r12, r0         # Propagate MSR_FP from SRR1 to MSR
         ori r12, r12, (MSR_IR | MSR_DR)@l
         mtsrr1 r12

kernel/arch/ppc32/src/fpu_context.S

@@ -29 +29 @@
 #include <arch/asm/regname.h>
 #include <arch/context_offset.h>
+#include <arch/msr.h>
 
 .text
@@ -39 +40 @@
 
 .macro FPU_CONTEXT_STORE r
+        stfd fr0, OFFSET_FR0(\r)
+        stfd fr1, OFFSET_FR1(\r)
+        stfd fr2, OFFSET_FR2(\r)
+        stfd fr3, OFFSET_FR3(\r)
+        stfd fr4, OFFSET_FR4(\r)
+        stfd fr5, OFFSET_FR5(\r)
+        stfd fr6, OFFSET_FR6(\r)
+        stfd fr7, OFFSET_FR7(\r)
+        stfd fr8, OFFSET_FR8(\r)
+        stfd fr9, OFFSET_FR9(\r)
+        stfd fr10, OFFSET_FR10(\r)
+        stfd fr11, OFFSET_FR11(\r)
+        stfd fr12, OFFSET_FR12(\r)
+        stfd fr13, OFFSET_FR13(\r)
         stfd fr14, OFFSET_FR14(\r)
         stfd fr15, OFFSET_FR15(\r)
@@ -60 +75 @@
 
 .macro FPU_CONTEXT_LOAD r
+        lfd fr0, OFFSET_FR0(\r)
+        lfd fr1, OFFSET_FR1(\r)
+        lfd fr2, OFFSET_FR2(\r)
+        lfd fr3, OFFSET_FR3(\r)
+        lfd fr4, OFFSET_FR4(\r)
+        lfd fr5, OFFSET_FR5(\r)
+        lfd fr6, OFFSET_FR6(\r)
+        lfd fr7, OFFSET_FR7(\r)
+        lfd fr8, OFFSET_FR8(\r)
+        lfd fr9, OFFSET_FR9(\r)
+        lfd fr10, OFFSET_FR10(\r)
+        lfd fr11, OFFSET_FR11(\r)
+        lfd fr12, OFFSET_FR12(\r)
+        lfd fr13, OFFSET_FR13(\r)
         lfd fr14, OFFSET_FR14(\r)
         lfd fr15, OFFSET_FR15(\r)
@@ -81 +110 @@
 
 fpu_context_save:
-//      FPU_CONTEXT_STORE r3
-//      
-//      mffs fr0
-//      stfd fr0, OFFSET_FPSCR(r3)
+        FPU_CONTEXT_STORE r3
+        
+        mffs fr0
+        stfd fr0, OFFSET_FPSCR(r3)
         
         blr
 
 fpu_context_restore:
-//      FPU_CONTEXT_LOAD r3
-//      
-//      lfd fr0, OFFSET_FPSCR(r3)
-//      mtfsf 7, fr0
+        lfd fr0, OFFSET_FPSCR(r3)
+        mtfsf 7, fr0
+
+        FPU_CONTEXT_LOAD r3
         
         blr
 
 fpu_init:
+        mfmsr r0
+        ori r0, r0, MSR_FP
+
+        # Disable FPU exceptions
+        li r3, MSR_FE0 | MSR_FE1
+        andc r0, r0, r3
+
+        mtmsr r0
         blr
 
 fpu_enable:
+        mfmsr r0
+        ori r0, r0, MSR_FP
+        mtmsr r0
         blr
 
 fpu_disable:
+        mfmsr r0
+        li r3, MSR_FP
+        andc r0, r0, r3
+        mtmsr r0
         blr
+

kernel/arch/ppc32/src/interrupt.c

@@ -112 +112 @@
 {
         uint8_t inum;
-        
+
         while ((inum = pic_get_pending()) != 255) {
                 irq_t *irq = irq_dispatch_and_lock(inum);
@@ -146 +146 @@
 }
 
+static void exception_fp_unavailable(unsigned int n, istate_t *istate)
+{
+#ifdef CONFIG_FPU_LAZY
+        scheduler_fpu_lazy_request();
+        /*
+         * Propagate MSR_FP from MSR back to istate's SRR1, which will become
+         * the next MSR.
+         */
+        istate->srr1 |= msr_read() & MSR_FP;
+#else
+        fault_if_from_uspace(istate, "FPU fault.");
+        panic_badtrap(istate, n, "FPU fault.");
+#endif
+}
+
 static void exception_decrementer(unsigned int n, istate_t *istate)
 {
@@ -161 +176 @@
         exc_register(VECTOR_EXTERNAL, "external", true,
             exception_external);
+        exc_register(VECTOR_FP_UNAVAILABLE, "fp_unavailable", true,
+            exception_fp_unavailable);
         exc_register(VECTOR_DECREMENTER, "timer", true,
             exception_decrementer);