Changeset dd0c8a0 in mainline for kernel/arch/arm32/src


Ignore:
Timestamp:
2013-09-29T06:56:33Z (12 years ago)
Author:
Beniamino Galvani <b.galvani@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
a9bd960d
Parents:
3deb0155 (diff), 13be2583 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/arm32/src
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/src/cpu/cpu.c

    r3deb0155 rdd0c8a0  
    157157#endif
    158158#ifdef PROCESSOR_ARCH_armv7_a
    159          /* ICache coherency is elaborate on in barrier.h.
     159         /* ICache coherency is elaborated on in barrier.h.
    160160          * VIPT and PIPT caches need maintenance only on code modify,
    161161          * so it should be safe for general use.
    … …  
    166166                control_reg |=
    167167                    SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
     168        } else {
     169                control_reg &=
     170                    ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG);
    168171        }
    169172#endif
    … …  
    204207#ifdef PROCESSOR_ARCH_armv7_a
    205208        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    206         const unsigned ls_log = 2 +
    207             ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK);
    208         return ls_log + 2; //return log2(bytes)
     209        const uint32_t ccsidr = CCSIDR_read();
     210        return CCSIDR_LINESIZE_LOG(ccsidr);
    209211#endif
    210212        return 0;
    … …  
    217219#ifdef PROCESSOR_ARCH_armv7_a
    218220        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    219         const unsigned ways = 1 +
    220             ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK);
    221         return ways;
     221        const uint32_t ccsidr = CCSIDR_read();
     222        return CCSIDR_WAYS(ccsidr);
    222223#endif
    223224        return 0;
    … …  
    229230#ifdef PROCESSOR_ARCH_armv7_a
    230231        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    231         const unsigned sets = 1 +
    232             ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK);
    233         return sets;
     232        const uint32_t ccsidr = CCSIDR_read();
     233        return CCSIDR_SETS(ccsidr);
    234234#endif
    235235        return 0;
    … …  
    241241#ifdef PROCESSOR_ARCH_armv7_a
    242242        const uint32_t val = CLIDR_read();
    243         for (unsigned i = 1; i <= 7; ++i) {
     243        for (unsigned i = 0; i < 8; ++i) {
    244244                const unsigned ctype = CLIDR_CACHE(i, val);
    245245                switch (ctype) {
    … …  
    280280                const unsigned ways = dcache_ways(i);
    281281                const unsigned sets = dcache_sets(i);
    282                 const unsigned way_shift =  31 - log2(ways);
     282                const unsigned way_shift = 32 - log2(ways);
    283283                const unsigned set_shift = dcache_linesize_log(i);
    284284                dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
    … …  
    293293                const unsigned ways = dcache_ways(i);
    294294                const unsigned sets = dcache_sets(i);
    295                 const unsigned way_shift =  31 - log2(ways);
     295                const unsigned way_shift = 32 - log2(ways);
    296296                const unsigned set_shift = dcache_linesize_log(i);
    297297                dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);

  • kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c

    r3deb0155 rdd0c8a0  
    6060
    6161static struct beagleboard {
    62         amdm37x_irc_regs_t *irc_addr;
    63         amdm37x_uart_t uart;
     62        omap_irc_regs_t *irc_addr;
     63        omap_uart_t uart;
    6464        amdm37x_gpt_t timer;
    6565} beagleboard;
    … …  
    8585static void bb_timer_irq_handler(irq_t *irq)
    8686{
     87        amdm37x_gpt_irq_ack(&beagleboard.timer);
     88
    8789        /*
    8890         * We are holding a lock which prevents preemption.
    8991         * Release the lock, call clock() and reacquire the lock again.
    9092         */
    91         amdm37x_gpt_irq_ack(&beagleboard.timer);
    9293        spinlock_unlock(&irq->lock);
    9394        clock();
    … …  
    102103            PAGE_NOT_CACHEABLE);
    103104        ASSERT(beagleboard.irc_addr);
    104         amdm37x_irc_init(beagleboard.irc_addr);
     105        omap_irc_init(beagleboard.irc_addr);
    105106
    106107        /* Initialize timer. Use timer1, because it is in WKUP power domain
    … …  
    122123
    123124        /* Enable timer interrupt */
    124         amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
     125        omap_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
    125126
    126127        /* Start timer here */
    … …  
    146147static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate)
    147148{
    148         const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
    149         amdm37x_irc_irq_ack(beagleboard.irc_addr);
     149        const unsigned inum = omap_irc_inum_get(beagleboard.irc_addr);
    150150
    151151        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    159159                    CPU->id, inum);
    160160        }
     161        /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
     162         * of ISR. DO this to avoid strange behavior. */
     163        omap_irc_irq_ack(beagleboard.irc_addr);
    161164}
    162165
    … …  
    167170static void bbxm_output_init(void)
    168171{
     172#ifdef CONFIG_OMAP_UART
    169173        /* UART3 is wired to external RS232 connector */
    170         const bool ok = amdm37x_uart_init(&beagleboard.uart,
     174        const bool ok = omap_uart_init(&beagleboard.uart,
    171175            AMDM37x_UART3_IRQ, AMDM37x_UART3_BASE_ADDRESS, AMDM37x_UART3_SIZE);
    172176        if (ok) {
    173177                stdout_wire(&beagleboard.uart.outdev);
    174178        }
     179#endif
    175180}
    176181
    177182static void bbxm_input_init(void)
    178183{
     184#ifdef CONFIG_OMAP_UART
    179185        srln_instance_t *srln_instance = srln_init();
    180186        if (srln_instance) {
    181187                indev_t *sink = stdin_wire();
    182188                indev_t *srln = srln_wire(srln_instance, sink);
    183                 amdm37x_uart_input_wire(&beagleboard.uart, srln);
    184                 amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
     189                omap_uart_input_wire(&beagleboard.uart, srln);
     190                omap_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
    185191        }
     192#endif
    186193}
    187194

  • kernel/arch/arm32/src/mach/beaglebone/beaglebone.c

    r3deb0155 rdd0c8a0  
    6363
    6464static struct beaglebone {
    65         am335x_irc_regs_t *irc_addr;
     65        omap_irc_regs_t *irc_addr;
    6666        am335x_cm_per_regs_t *cm_per_addr;
    6767        am335x_cm_dpll_regs_t *cm_dpll_addr;
    6868        am335x_ctrl_module_t  *ctrl_module;
    6969        am335x_timer_t timer;
    70         am335x_uart_t uart;
     70        omap_uart_t uart;
    7171} bbone;
    7272
    … …  
    104104
    105105        /* Initialize the interrupt controller */
    106         am335x_irc_init(bbone.irc_addr);
     106        omap_irc_init(bbone.irc_addr);
    107107}
    108108
    … …  
    153153        }
    154154        /* Enable the interrupt */
    155         am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
     155        omap_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
    156156        /* Start the timer */
    157157        am335x_timer_start(&bbone.timer);
    … …  
    176176static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
    177177{
    178         const unsigned inum = am335x_irc_inum_get(bbone.irc_addr);
    179         am335x_irc_irq_ack(bbone.irc_addr);
     178        const unsigned inum = omap_irc_inum_get(bbone.irc_addr);
    180179
    181180        irq_t *irq = irq_dispatch_and_lock(inum);
    … …  
    187186                printf("Spurious interrupt\n");
    188187        }
     188
     189        omap_irc_irq_ack(bbone.irc_addr);
    189190}
    190191
    … …  
    195196static void bbone_output_init(void)
    196197{
    197         const bool ok = am335x_uart_init(&bbone.uart,
     198#ifdef CONFIG_OMAP_UART
     199        const bool ok = omap_uart_init(&bbone.uart,
    198200            AM335x_UART0_IRQ, AM335x_UART0_BASE_ADDRESS,
    199201            AM335x_UART0_SIZE);
    … …  
    201203        if (ok)
    202204                stdout_wire(&bbone.uart.outdev);
     205#endif
    203206}
    204207
    205208static void bbone_input_init(void)
    206209{
     210#ifdef CONFIG_OMAP_UART
    207211        srln_instance_t *srln_instance = srln_init();
    208212        if (srln_instance) {
    209213                indev_t *sink = stdin_wire();
    210214                indev_t *srln = srln_wire(srln_instance, sink);
    211                 am335x_uart_input_wire(&bbone.uart, srln);
    212                 am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
     215                omap_uart_input_wire(&bbone.uart, srln);
     216                omap_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
    213217        }
     218#endif
    214219}
    215220

  • kernel/arch/arm32/src/mm/frame.c

    r3deb0155 rdd0c8a0  
    8888void boot_page_table_free(void)
    8989{
    90         unsigned int i;
    91         for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++)
    92                 frame_free(i * FRAME_SIZE + BOOT_PAGE_TABLE_ADDRESS);
     90        frame_free(BOOT_PAGE_TABLE_ADDRESS,
     91            BOOT_PAGE_TABLE_SIZE_IN_FRAMES);
    9392}
    9493

  • kernel/arch/arm32/src/mm/page.c

    r3deb0155 rdd0c8a0  
    7373#ifdef HIGH_EXCEPTION_VECTORS
    7474        /* Create mapping for exception table at high offset */
    75         uintptr_t ev_frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_NONE);
     75        uintptr_t ev_frame = frame_alloc(1, FRAME_NONE, 0);
    7676        page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, ev_frame, flags);
    7777#else

  • kernel/arch/arm32/src/mm/tlb.c

    r3deb0155 rdd0c8a0  
    3737#include <arch/mm/asid.h>
    3838#include <arch/asm.h>
     39#include <arch/cp15.h>
    3940#include <typedefs.h>
    4041#include <arch/mm/page.h>
     42#include <arch/cache.h>
    4143
    4244/** Invalidate all entries in TLB.
    … …  
    4648void tlb_invalidate_all(void)
    4749{
    48         asm volatile (
    49                 "eor r1, r1\n"
    50                 "mcr p15, 0, r1, c8, c7, 0\n"
    51                 ::: "r1"
    52         );
     50        TLBIALL_write(0);
     51        /*
     52         * "A TLB maintenance operation is only guaranteed to be complete after
     53         * the execution of a DSB instruction."
     54         * "An ISB instruction, or a return from an exception, causes the
     55         * effect of all completed TLB maintenance operations that appear in
     56         * program order before the ISB or return from exception to be visible
     57         * to all subsequent instructions, including the instruction fetches
     58         * for those instructions."
     59         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
     60         */
     61        read_barrier();
     62        inst_barrier();
    5363}
    5464
    … …  
    6070{
    6171        tlb_invalidate_all();
     72        // TODO: why not TLBIASID_write(asid) ?
    6273}
    6374
    … …  
    6576 *
    6677 * @param page Virtual adress of the page
    67  */ 
     78 */
    6879static inline void invalidate_page(uintptr_t page)
    6980{
    70         asm volatile (
    71                 "mcr p15, 0, %[page], c8, c7, 1\n"
    72                 :: [page] "r" (page)
    73         );
     81        //TODO: What about TLBIMVAA?
     82        TLBIMVA_write(page);
     83        /*
     84         * "A TLB maintenance operation is only guaranteed to be complete after
     85         * the execution of a DSB instruction."
     86         * "An ISB instruction, or a return from an exception, causes the
     87         * effect of all completed TLB maintenance operations that appear in
     88         * program order before the ISB or return from exception to be visible
     89         * to all subsequent instructions, including the instruction fetches
     90         * for those instructions."
     91         * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375
     92         */
     93        read_barrier();
     94        inst_barrier();
    7495}
    7596
    … …  
    83104void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt)
    84105{
    85         unsigned int i;
    86 
    87         for (i = 0; i < cnt; i++)
     106        for (unsigned i = 0; i < cnt; i++)
    88107                invalidate_page(page + i * PAGE_SIZE);
    89108}

  • kernel/arch/arm32/src/ras.c

    r3deb0155 rdd0c8a0  
    5151void ras_init(void)
    5252{
    53         uintptr_t frame;
    54 
    55         frame = (uintptr_t) frame_alloc(ONE_FRAME,
    56             FRAME_ATOMIC | FRAME_HIGHMEM);
     53        uintptr_t frame =
     54            frame_alloc(1, FRAME_ATOMIC | FRAME_HIGHMEM, 0);
    5755        if (!frame)
    58                 frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_LOWMEM);
     56                frame = frame_alloc(1, FRAME_LOWMEM, 0);
     57       
    5958        ras_page = (uintptr_t *) km_map(frame,
    6059            PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
    61 
     60       
    6261        memsetb(ras_page, PAGE_SIZE, 0);
    6362        ras_page[RAS_START] = 0;
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