Index: kernel/arch/ia32/include/boot/boot.h =================================================================== --- kernel/arch/ia32/include/boot/boot.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/boot/boot.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -38,5 +38,5 @@ #define BOOT_OFFSET 0x108000 #define AP_BOOT_OFFSET 0x8000 -#define BOOT_STACK_SIZE 0x400 +#define BOOT_STACK_SIZE 0x0400 #define MULTIBOOT_HEADER_MAGIC 0x1BADB002 Index: kernel/arch/ia32/include/boot/memmap.h =================================================================== --- kernel/arch/ia32/include/boot/memmap.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/boot/memmap.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -70,5 +70,5 @@ extern e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS]; -extern uint8_t e820counter; +extern uint8_t e820counter; #endif Index: kernel/arch/ia32/include/context.h =================================================================== --- kernel/arch/ia32/include/context.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/context.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -40,5 +40,5 @@ #include -#define STACK_ITEM_SIZE 4 +#define STACK_ITEM_SIZE 4 /* @@ -48,5 +48,5 @@ * One item is put onto stack to support get_stack_base(). */ -#define SP_DELTA (8 + STACK_ITEM_SIZE) +#define SP_DELTA (8 + STACK_ITEM_SIZE) #define context_set(c, _pc, stack, size) \ Index: kernel/arch/ia32/include/context_offset.h =================================================================== --- kernel/arch/ia32/include/context_offset.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/context_offset.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ @@ -36,33 +36,32 @@ #define KERN_ia32_CONTEXT_OFFSET_H_ -#define OFFSET_SP 0x0 -#define OFFSET_PC 0x4 -#define OFFSET_EBX 0x8 -#define OFFSET_ESI 0xC -#define OFFSET_EDI 0x10 -#define OFFSET_EBP 0x14 +#define OFFSET_SP 0x00 +#define OFFSET_PC 0x04 +#define OFFSET_EBX 0x08 +#define OFFSET_ESI 0x0C +#define OFFSET_EDI 0x10 +#define OFFSET_EBP 0x14 -#ifdef KERNEL -# define OFFSET_IPL 0x18 +#ifdef KERNEL + #define OFFSET_IPL 0x18 #else -# define OFFSET_TLS 0x18 + #define OFFSET_TLS 0x18 #endif +#ifdef __ASM__ -#ifdef __ASM__ - -# ctx: address of the structure with saved context +# ctx: address of the structure with saved context # pc: return address .macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req - movl %esp,OFFSET_SP(\ctx) # %esp -> ctx->sp + movl %esp,OFFSET_SP(\ctx) # %esp -> ctx->sp movl \pc,OFFSET_PC(\ctx) # %eip -> ctx->pc - movl %ebx,OFFSET_EBX(\ctx) # %ebx -> ctx->ebx - movl %esi,OFFSET_ESI(\ctx) # %esi -> ctx->esi - movl %edi,OFFSET_EDI(\ctx) # %edi -> ctx->edi - movl %ebp,OFFSET_EBP(\ctx) # %ebp -> ctx->ebp + movl %ebx,OFFSET_EBX(\ctx) # %ebx -> ctx->ebx + movl %esi,OFFSET_ESI(\ctx) # %esi -> ctx->esi + movl %edi,OFFSET_EDI(\ctx) # %edi -> ctx->edi + movl %ebp,OFFSET_EBP(\ctx) # %ebp -> ctx->ebp .endm -# ctx: address of the structure with saved context +# ctx: address of the structure with saved context .macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req @@ -75,5 +74,5 @@ .endm -#endif /* __ASM__ */ +#endif /* __ASM__ */ #endif @@ -81,3 +80,2 @@ /** @} */ - Index: kernel/arch/ia32/include/cpu.h =================================================================== --- kernel/arch/ia32/include/cpu.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/cpu.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -44,7 +44,7 @@ /* Support for SYSENTER and SYSEXIT */ -#define IA32_MSR_SYSENTER_CS 0x174 -#define IA32_MSR_SYSENTER_ESP 0x175 -#define IA32_MSR_SYSENTER_EIP 0x176 +#define IA32_MSR_SYSENTER_CS 0x174U +#define IA32_MSR_SYSENTER_ESP 0x175U +#define IA32_MSR_SYSENTER_EIP 0x176U #ifndef __ASM__ Index: kernel/arch/ia32/include/drivers/i8259.h =================================================================== --- kernel/arch/ia32/include/drivers/i8259.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/drivers/i8259.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -39,8 +39,8 @@ #include -#define PIC_PIC0PORT1 ((ioport8_t *) 0x20) -#define PIC_PIC0PORT2 ((ioport8_t *) 0x21) -#define PIC_PIC1PORT1 ((ioport8_t *) 0xa0) -#define PIC_PIC1PORT2 ((ioport8_t *) 0xa1) +#define PIC_PIC0PORT1 ((ioport8_t *) 0x20U) +#define PIC_PIC0PORT2 ((ioport8_t *) 0x21U) +#define PIC_PIC1PORT1 ((ioport8_t *) 0xa0U) +#define PIC_PIC1PORT2 ((ioport8_t *) 0xa1U) #define PIC_NEEDICW4 (1 << 0) Index: kernel/arch/ia32/include/istate.h =================================================================== --- kernel/arch/ia32/include/istate.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/istate.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -37,10 +37,15 @@ #ifdef KERNEL + #include #include -#else + +#else /* KERNEL */ + #include + #define NO_TRACE -#endif + +#endif /* KERNEL */ typedef struct istate { @@ -77,5 +82,5 @@ NO_TRACE static inline int istate_from_uspace(istate_t *istate) { - return !(istate->eip & 0x80000000); + return !(istate->eip & UINT32_C(0x80000000)); } Index: kernel/arch/ia32/include/mm/as.h =================================================================== --- kernel/arch/ia32/include/mm/as.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/mm/as.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -36,12 +36,12 @@ #define KERN_ia32_AS_H_ -#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 -#define KERNEL_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x80000000) -#define KERNEL_ADDRESS_SPACE_END_ARCH ((unsigned long) 0xffffffff) -#define USER_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x00000000) -#define USER_ADDRESS_SPACE_END_ARCH ((unsigned long) 0x7fffffff) +#define KERNEL_ADDRESS_SPACE_START_ARCH UINT32_C(0x80000000) +#define KERNEL_ADDRESS_SPACE_END_ARCH UINT32_C(0xffffffff) +#define USER_ADDRESS_SPACE_START_ARCH UINT32_C(0x00000000) +#define USER_ADDRESS_SPACE_END_ARCH UINT32_C(0x7fffffff) -#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1)) +#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1)) typedef struct { @@ -50,7 +50,7 @@ #include -#define as_constructor_arch(as, flags) (as != as) -#define as_destructor_arch(as) (as != as) -#define as_create_arch(as, flags) (as != as) +#define as_constructor_arch(as, flags) (as != as) +#define as_destructor_arch(as) (as != as) +#define as_create_arch(as, flags) (as != as) #define as_install_arch(as) #define as_deinstall_arch(as) Index: kernel/arch/ia32/include/mm/page.h =================================================================== --- kernel/arch/ia32/include/mm/page.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/mm/page.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -39,16 +39,20 @@ #include -#define PAGE_WIDTH FRAME_WIDTH -#define PAGE_SIZE FRAME_SIZE +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE #ifdef KERNEL #ifndef __ASM__ -# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) -# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) -#else -# define KA2PA(x) ((x) - 0x80000000) -# define PA2KA(x) ((x) + 0x80000000) -#endif + +#define KA2PA(x) (((uintptr_t) (x)) - UINT32_C(0x80000000)) +#define PA2KA(x) (((uintptr_t) (x)) + UINT32_C(0x80000000)) + +#else /* __ASM__ */ + +#define KA2PA(x) ((x) - 0x80000000) +#define PA2KA(x) ((x) + 0x80000000) + +#endif /* __ASM__ */ /* @@ -58,20 +62,20 @@ /* Number of entries in each level. */ -#define PTL0_ENTRIES_ARCH 1024 -#define PTL1_ENTRIES_ARCH 0 -#define PTL2_ENTRIES_ARCH 0 -#define PTL3_ENTRIES_ARCH 1024 +#define PTL0_ENTRIES_ARCH 1024 +#define PTL1_ENTRIES_ARCH 0 +#define PTL2_ENTRIES_ARCH 0 +#define PTL3_ENTRIES_ARCH 1024 /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_SIZE_ARCH ONE_FRAME +#define PTL1_SIZE_ARCH 0 +#define PTL2_SIZE_ARCH 0 +#define PTL3_SIZE_ARCH ONE_FRAME /* Macros calculating indices for each level. */ -#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) -#define PTL1_INDEX_ARCH(vaddr) 0 -#define PTL2_INDEX_ARCH(vaddr) 0 -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) +#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ffU) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ffU) /* Get PTE address accessors for each level. */ @@ -122,5 +126,5 @@ #define PTE_WRITABLE_ARCH(p) \ ((p)->writeable != 0) -#define PTE_EXECUTABLE_ARCH(p) 1 +#define PTE_EXECUTABLE_ARCH(p) 1 #ifndef __ASM__ @@ -144,5 +148,5 @@ /** When bit on this position is 1, a reserved bit was set in page directory. */ -#define PFERR_CODE_RSVD (1 << 3) +#define PFERR_CODE_RSVD (1 << 3) /** Page Table Entry. */ Index: kernel/arch/ia32/include/smp/ap.h =================================================================== --- kernel/arch/ia32/include/smp/ap.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/smp/ap.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -27,5 +27,5 @@ */ -/** @addtogroup ia32 +/** @addtogroup ia32 * @{ */ Index: kernel/arch/ia32/include/smp/apic.h =================================================================== --- kernel/arch/ia32/include/smp/apic.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/smp/apic.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -49,63 +49,63 @@ /** Delivery modes. */ -#define DELMOD_FIXED 0x0 -#define DELMOD_LOWPRI 0x1 -#define DELMOD_SMI 0x2 +#define DELMOD_FIXED 0x0U +#define DELMOD_LOWPRI 0x1U +#define DELMOD_SMI 0x2U /* 0x3 reserved */ -#define DELMOD_NMI 0x4 -#define DELMOD_INIT 0x5 -#define DELMOD_STARTUP 0x6 -#define DELMOD_EXTINT 0x7 +#define DELMOD_NMI 0x4U +#define DELMOD_INIT 0x5U +#define DELMOD_STARTUP 0x6U +#define DELMOD_EXTINT 0x7U /** Destination modes. */ -#define DESTMOD_PHYS 0x0 -#define DESTMOD_LOGIC 0x1 +#define DESTMOD_PHYS 0x0U +#define DESTMOD_LOGIC 0x1U /** Trigger Modes. */ -#define TRIGMOD_EDGE 0x0 -#define TRIGMOD_LEVEL 0x1 +#define TRIGMOD_EDGE 0x0U +#define TRIGMOD_LEVEL 0x1U /** Levels. */ -#define LEVEL_DEASSERT 0x0 -#define LEVEL_ASSERT 0x1 +#define LEVEL_DEASSERT 0x0U +#define LEVEL_ASSERT 0x1U /** Destination Shorthands. */ -#define SHORTHAND_NONE 0x0 -#define SHORTHAND_SELF 0x1 -#define SHORTHAND_ALL_INCL 0x2 -#define SHORTHAND_ALL_EXCL 0x3 +#define SHORTHAND_NONE 0x0U +#define SHORTHAND_SELF 0x1U +#define SHORTHAND_ALL_INCL 0x2U +#define SHORTHAND_ALL_EXCL 0x3U /** Interrupt Input Pin Polarities. */ -#define POLARITY_HIGH 0x0 -#define POLARITY_LOW 0x1 +#define POLARITY_HIGH 0x0U +#define POLARITY_LOW 0x1U /** Divide Values. (Bit 2 is always 0) */ -#define DIVIDE_2 0x0 -#define DIVIDE_4 0x1 -#define DIVIDE_8 0x2 -#define DIVIDE_16 0x3 -#define DIVIDE_32 0x8 -#define DIVIDE_64 0x9 -#define DIVIDE_128 0xa -#define DIVIDE_1 0xb +#define DIVIDE_2 0x0U +#define DIVIDE_4 0x1U +#define DIVIDE_8 0x2U +#define DIVIDE_16 0x3U +#define DIVIDE_32 0x8U +#define DIVIDE_64 0x9U +#define DIVIDE_128 0xaU +#define DIVIDE_1 0xbU /** Timer Modes. */ -#define TIMER_ONESHOT 0x0 -#define TIMER_PERIODIC 0x1 +#define TIMER_ONESHOT 0x0U +#define TIMER_PERIODIC 0x1U /** Delivery status. */ -#define DELIVS_IDLE 0x0 -#define DELIVS_PENDING 0x1 +#define DELIVS_IDLE 0x0U +#define DELIVS_PENDING 0x1U /** Destination masks. */ -#define DEST_ALL 0xff +#define DEST_ALL 0xffU /** Dest format models. */ -#define MODEL_FLAT 0xf -#define MODEL_CLUSTER 0x0 +#define MODEL_FLAT 0xfU +#define MODEL_CLUSTER 0x0U /** Interrupt Command Register. */ -#define ICRlo (0x300 / sizeof(uint32_t)) -#define ICRhi (0x310 / sizeof(uint32_t)) +#define ICRlo (0x300U / sizeof(uint32_t)) +#define ICRhi (0x310U / sizeof(uint32_t)) typedef struct { @@ -135,8 +135,8 @@ /* End Of Interrupt. */ -#define EOI (0x0b0 / sizeof(uint32_t)) +#define EOI (0x0b0U / sizeof(uint32_t)) /** Error Status Register. */ -#define ESR (0x280 / sizeof(uint32_t)) +#define ESR (0x280U / sizeof(uint32_t)) typedef union { @@ -157,5 +157,5 @@ /* Task Priority Register */ -#define TPR (0x080 / sizeof(uint32_t)) +#define TPR (0x080U / sizeof(uint32_t)) typedef union { @@ -168,5 +168,5 @@ /** Spurious-Interrupt Vector Register. */ -#define SVR (0x0f0 / sizeof(uint32_t)) +#define SVR (0x0f0U / sizeof(uint32_t)) typedef union { @@ -181,5 +181,5 @@ /** Time Divide Configuration Register. */ -#define TDCR (0x3e0 / sizeof(uint32_t)) +#define TDCR (0x3e0U / sizeof(uint32_t)) typedef union { @@ -192,11 +192,11 @@ /* Initial Count Register for Timer */ -#define ICRT (0x380 / sizeof(uint32_t)) +#define ICRT (0x380U / sizeof(uint32_t)) /* Current Count Register for Timer */ -#define CCRT (0x390 / sizeof(uint32_t)) +#define CCRT (0x390U / sizeof(uint32_t)) /** LVT Timer register. */ -#define LVT_Tm (0x320 / sizeof(uint32_t)) +#define LVT_Tm (0x320U / sizeof(uint32_t)) typedef union { @@ -214,6 +214,6 @@ /** LVT LINT registers. */ -#define LVT_LINT0 (0x350 / sizeof(uint32_t)) -#define LVT_LINT1 (0x360 / sizeof(uint32_t)) +#define LVT_LINT0 (0x350U / sizeof(uint32_t)) +#define LVT_LINT1 (0x360U / sizeof(uint32_t)) typedef union { @@ -233,5 +233,5 @@ /** LVT Error register. */ -#define LVT_Err (0x370 / sizeof(uint32_t)) +#define LVT_Err (0x370U / sizeof(uint32_t)) typedef union { @@ -248,5 +248,5 @@ /** Local APIC ID Register. */ -#define L_APIC_ID (0x020 / sizeof(uint32_t)) +#define L_APIC_ID (0x020U / sizeof(uint32_t)) typedef union { @@ -259,13 +259,13 @@ /** Local APIC Version Register */ -#define LAVR (0x030 / sizeof(uint32_t)) -#define LAVR_Mask 0xff - -#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1) -#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0)) -#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14) +#define LAVR (0x030U / sizeof(uint32_t)) +#define LAVR_Mask 0xffU + +#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0U) == 0x1U) +#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0U) == 0x0U)) +#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14U) /** Logical Destination Register. */ -#define LDR (0x0d0 / sizeof(uint32_t)) +#define LDR (0x0d0U / sizeof(uint32_t)) typedef union { @@ -278,5 +278,5 @@ /** Destination Format Register. */ -#define DFR (0x0e0 / sizeof(uint32_t)) +#define DFR (0x0e0U / sizeof(uint32_t)) typedef union { @@ -289,11 +289,11 @@ /* IO APIC */ -#define IOREGSEL (0x00 / sizeof(uint32_t)) -#define IOWIN (0x10 / sizeof(uint32_t)) - -#define IOAPICID 0x00 -#define IOAPICVER 0x01 -#define IOAPICARB 0x02 -#define IOREDTBL 0x10 +#define IOREGSEL (0x00U / sizeof(uint32_t)) +#define IOWIN (0x10U / sizeof(uint32_t)) + +#define IOAPICID 0x00U +#define IOAPICVER 0x01U +#define IOAPICARB 0x02U +#define IOREDTBL 0x10U /** I/O Register Select Register. */ Index: kernel/arch/ia32/include/types.h =================================================================== --- kernel/arch/ia32/include/types.h (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/include/types.h (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -50,24 +50,9 @@ } fncptr_t; -#define PRIp "x" /**< Format for uintptr_t. */ -#define PRIs "u" /**< Format for size_t. */ - -#define PRId8 "d" /**< Format for int8_t. */ -#define PRId16 "d" /**< Format for int16_t. */ -#define PRId32 "d" /**< Format for int32_t. */ -#define PRId64 "lld" /**< Format for int64_t. */ -#define PRIdn "d" /**< Format for native_t. */ - -#define PRIu8 "u" /**< Format for uint8_t. */ -#define PRIu16 "u" /**< Format for uint16_t. */ -#define PRIu32 "u" /**< Format for uint32_t. */ -#define PRIu64 "llu" /**< Format for uint64_t. */ -#define PRIun "u" /**< Format for unative_t. */ - -#define PRIx8 "x" /**< Format for hexadecimal (u)int8_t. */ -#define PRIx16 "x" /**< Format for hexadecimal (u)int16_t. */ -#define PRIx32 "x" /**< Format for hexadecimal (u)uint32_t. */ -#define PRIx64 "llx" /**< Format for hexadecimal (u)int64_t. */ -#define PRIxn "x" /**< Format for hexadecimal (u)native_t. */ +#define PRIp PRIx32 /**< Format for uintptr_t. */ +#define PRIs PRIu32 /**< Format for size_t. */ +#define PRIdn PRId32 /**< Format for native_t. */ +#define PRIun PRIu32 /**< Format for unative_t. */ +#define PRIxn PRIx32 /**< Format for hexadecimal unative_t. */ #endif Index: kernel/arch/ia32/src/bios/bios.c =================================================================== --- kernel/arch/ia32/src/bios/bios.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/bios/bios.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -36,5 +36,5 @@ #include -#define BIOS_EBDA_PTR 0x40e +#define BIOS_EBDA_PTR 0x40eU uintptr_t ebda = 0; @@ -43,5 +43,5 @@ { /* Copy the EBDA address out from BIOS Data Area */ - ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10; + ebda = *((uint16_t *) BIOS_EBDA_PTR) * 0x10U; } Index: kernel/arch/ia32/src/boot/memmap.c =================================================================== --- kernel/arch/ia32/src/boot/memmap.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/boot/memmap.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -35,5 +35,5 @@ #include -uint8_t e820counter = 0xff; +uint8_t e820counter = 0xffU; e820memmap_t e820table[MEMMAP_E820_MAX_RECORDS]; Index: kernel/arch/ia32/src/cpu/cpu.c =================================================================== --- kernel/arch/ia32/src/cpu/cpu.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/cpu/cpu.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -49,11 +49,11 @@ * Contains only non-MP-Specification specific SMP code. */ -#define AMD_CPUID_EBX 0x68747541 -#define AMD_CPUID_ECX 0x444d4163 -#define AMD_CPUID_EDX 0x69746e65 +#define AMD_CPUID_EBX UINT32_C(0x68747541) +#define AMD_CPUID_ECX UINT32_C(0x444d4163) +#define AMD_CPUID_EDX UINT32_C(0x69746e65) -#define INTEL_CPUID_EBX 0x756e6547 -#define INTEL_CPUID_ECX 0x6c65746e -#define INTEL_CPUID_EDX 0x49656e69 +#define INTEL_CPUID_EBX UINT32_C(0x756e6547) +#define INTEL_CPUID_ECX UINT32_C(0x6c65746e) +#define INTEL_CPUID_EDX UINT32_C(0x49656e69) @@ -140,19 +140,19 @@ if ((info.cpuid_ebx == AMD_CPUID_EBX) && (info.cpuid_ecx == AMD_CPUID_ECX) - && (info.cpuid_edx == AMD_CPUID_EDX)) + && (info.cpuid_edx == AMD_CPUID_EDX)) CPU->arch.vendor = VendorAMD; /* * Check for Intel processor. - */ + */ if ((info.cpuid_ebx == INTEL_CPUID_EBX) && (info.cpuid_ecx == INTEL_CPUID_ECX) - && (info.cpuid_edx == INTEL_CPUID_EDX)) + && (info.cpuid_edx == INTEL_CPUID_EDX)) CPU->arch.vendor = VendorIntel; cpuid(INTEL_CPUID_STANDARD, &info); - CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f; - CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f; - CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f; + CPU->arch.family = (info.cpuid_eax >> 8) & 0x0fU; + CPU->arch.model = (info.cpuid_eax >> 4) & 0x0fU; + CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0fU; } } Index: kernel/arch/ia32/src/debug/stacktrace.c =================================================================== --- kernel/arch/ia32/src/debug/stacktrace.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/debug/stacktrace.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -37,6 +37,6 @@ #include -#define FRAME_OFFSET_FP_PREV 0 -#define FRAME_OFFSET_RA 1 +#define FRAME_OFFSET_FP_PREV 0 +#define FRAME_OFFSET_RA 1 bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx) Index: kernel/arch/ia32/src/drivers/i8254.c =================================================================== --- kernel/arch/ia32/src/drivers/i8254.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/drivers/i8254.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -54,6 +54,6 @@ #include -#define CLK_PORT1 ((ioport8_t *) 0x40) -#define CLK_PORT4 ((ioport8_t *) 0x43) +#define CLK_PORT1 ((ioport8_t *) 0x40U) +#define CLK_PORT4 ((ioport8_t *) 0x43U) #define CLK_CONST 1193180 Index: kernel/arch/ia32/src/drivers/i8259.c =================================================================== --- kernel/arch/ia32/src/drivers/i8259.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/drivers/i8259.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -121,6 +121,6 @@ void pic_eoi(void) { - pio_write_8((ioport8_t *)0x20, 0x20); - pio_write_8((ioport8_t *)0xa0, 0x20); + pio_write_8((ioport8_t *) 0x20, 0x20); + pio_write_8((ioport8_t *) 0xa0, 0x20); } Index: kernel/arch/ia32/src/drivers/vesa.c =================================================================== --- kernel/arch/ia32/src/drivers/vesa.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/drivers/vesa.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -70,5 +70,5 @@ bool vesa_init(void) { - if ((vesa_width == 0xffff) || (vesa_height == 0xffff)) + if ((vesa_width == 0xffffU) || (vesa_height == 0xffffU)) return false; Index: kernel/arch/ia32/src/mm/frame.c =================================================================== --- kernel/arch/ia32/src/mm/frame.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/mm/frame.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -44,9 +44,8 @@ #include #include - #include -#define PHYSMEM_LIMIT32 0x07c000000ull -#define PHYSMEM_LIMIT64 0x200000000ull +#define PHYSMEM_LIMIT32 UINT64_C(0x07c000000) +#define PHYSMEM_LIMIT64 UINT64_C(0x200000000) size_t hardcoded_unmapped_ktext_size = 0; Index: kernel/arch/ia32/src/smp/apic.c =================================================================== --- kernel/arch/ia32/src/smp/apic.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/smp/apic.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -72,6 +72,6 @@ * */ -volatile uint32_t *l_apic = (uint32_t *) 0xfee00000; -volatile uint32_t *io_apic = (uint32_t *) 0xfec00000; +volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000); +volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000); uint32_t apic_id_mask = 0; @@ -184,5 +184,5 @@ * Other interrupts will be forwarded to the lowest priority CPU. */ - io_apic_disable_irqs(0xffff); + io_apic_disable_irqs(0xffffU); irq_initialize(&l_apic_timer_irq); Index: kernel/arch/ia32/src/smp/mps.c =================================================================== --- kernel/arch/ia32/src/smp/mps.c (revision e9e5b9ab0ff1b3bcb98d019c57dddaee8b071601) +++ kernel/arch/ia32/src/smp/mps.c (revision dc0b96419120ee5e704d73292cca782d65f45781) @@ -52,6 +52,6 @@ */ -#define FS_SIGNATURE 0x5f504d5f -#define CT_SIGNATURE 0x504d4350 +#define FS_SIGNATURE UINT32_C(0x5f504d5f) +#define CT_SIGNATURE UINT32_C(0x504d4350) static struct mps_fs *fs;