Changes in kernel/arch/ppc32/include/asm.h [3500f75:d99c1d2] in mainline

File:

• kernel/arch/ppc32/include/asm.h (modified) (6 diffs)

kernel/arch/ppc32/include/asm.h

@@ -38 +38 @@
 #include <typedefs.h>
 #include <config.h>
-#include <arch/cpu.h>
-
-static inline uint32_t msr_read(void)
-{
-        uint32_t msr;
-        
-        asm volatile (
-                "mfmsr %[msr]\n"
-                : [msr] "=r" (msr)
-        );
-        
-        return msr;
-}
-
-static inline void msr_write(uint32_t msr)
-{
-        asm volatile (
-                "mtmsr %[msr]\n"
-                :: [msr] "r" (msr)
-        );
-}
 
 /** Enable interrupts.
@@ -66 +45 @@
  *
  * @return Old interrupt priority level.
- *
  */
 static inline ipl_t interrupts_enable(void)
 {
-        ipl_t ipl = msr_read();
-        msr_write(ipl | MSR_EE);
-        return ipl;
+        ipl_t v;
+        ipl_t tmp;
+        
+        asm volatile (
+                "mfmsr %0\n"
+                "mfmsr %1\n"
+                "ori %1, %1, 1 << 15\n"
+                "mtmsr %1\n"
+                : "=r" (v), "=r" (tmp)
+        );
+        return v;
 }
 
@@ -81 +67 @@
  *
  * @return Old interrupt priority level.
- *
  */
 static inline ipl_t interrupts_disable(void)
 {
-        ipl_t ipl = msr_read();
-        msr_write(ipl & (~MSR_EE));
-        return ipl;
+        ipl_t v;
+        ipl_t tmp;
+        
+        asm volatile (
+                "mfmsr %0\n"
+                "mfmsr %1\n"
+                "rlwinm %1, %1, 0, 17, 15\n"
+                "mtmsr %1\n"
+                : "=r" (v), "=r" (tmp)
+        );
+        return v;
 }
 
@@ -95 +88 @@
  *
  * @param ipl Saved interrupt priority level.
- *
  */
 static inline void interrupts_restore(ipl_t ipl)
 {
-        msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE));
+        ipl_t tmp;
+        
+        asm volatile (
+                "mfmsr %1\n"
+                "rlwimi  %0, %1, 0, 17, 15\n"
+                "cmpw 0, %0, %1\n"
+                "beq 0f\n"
+                "mtmsr %0\n"
+                "0:\n"
+                : "=r" (ipl), "=r" (tmp)
+                : "0" (ipl)
+                : "cr0"
+        );
 }
 
@@ -107 +111 @@
  *
  * @return Current interrupt priority level.
- *
  */
 static inline ipl_t interrupts_read(void)
 {
-        return msr_read();
-}
-
-/** Check whether interrupts are disabled.
- *
- * @return True if interrupts are disabled.
- *
- */
-static inline bool interrupts_disabled(void)
-{
-        return ((msr_read() & MSR_EE) == 0);
+        ipl_t v;
+        
+        asm volatile (
+                "mfmsr %0\n"
+                : "=r" (v)
+        );
+        return v;
 }
 
@@ -129 +128 @@
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
- *
  */
 static inline uintptr_t get_stack_base(void)
 {
-        uintptr_t base;
+        uintptr_t v;
         
         asm volatile (
-                "and %[base], %%sp, %[mask]\n"
-                : [base] "=r" (base)
-                : [mask] "r" (~(STACK_SIZE - 1))
+                "and %0, %%sp, %1\n"
+                : "=r" (v)
+                : "r" (~(STACK_SIZE - 1))
         );
-        
-        return base;
+        return v;
 }