Index: kernel/arch/mips32/include/cp0.h =================================================================== --- kernel/arch/mips32/include/cp0.h (revision d354d57caee72a5cbe1a16c069ff43d067f07966) +++ kernel/arch/mips32/include/cp0.h (revision d92bf462a666dbc8e25bc56006b03724997951c4) @@ -38,10 +38,10 @@ #include -#define cp0_status_ie_enabled_bit (1 << 0) -#define cp0_status_exl_exception_bit (1 << 1) -#define cp0_status_erl_error_bit (1 << 2) -#define cp0_status_um_bit (1 << 4) -#define cp0_status_bev_bootstrap_bit (1 << 22) -#define cp0_status_fpu_bit (1 << 29) +#define cp0_status_ie_enabled_bit (1 << 0) +#define cp0_status_exl_exception_bit (1 << 1) +#define cp0_status_erl_error_bit (1 << 2) +#define cp0_status_um_bit (1 << 4) +#define cp0_status_bev_bootstrap_bit (1 << 22) +#define cp0_status_fpu_bit (1 << 29) #define cp0_status_im_shift 8 Index: kernel/arch/mips32/src/start.S =================================================================== --- kernel/arch/mips32/src/start.S (revision d354d57caee72a5cbe1a16c069ff43d067f07966) +++ kernel/arch/mips32/src/start.S (revision d92bf462a666dbc8e25bc56006b03724997951c4) @@ -47,9 +47,9 @@ # Which status bits should are thread-local #define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE - + # Save registers to space defined by \r -# We will change status: Disable ERL,EXL,UM,IE +# We will change status: Disable ERL, EXL, UM, IE # These changes will be automatically reversed in REGISTER_LOAD -# SP is NOT saved as part of these registers +# %sp is NOT saved as part of these registers .macro REGISTERS_STORE_AND_EXC_RESET r sw $at, EOFFSET_AT(\r) @@ -70,5 +70,5 @@ sw $t8, EOFFSET_T8(\r) sw $t9, EOFFSET_T9(\r) - + mflo $at sw $at, EOFFSET_LO(\r) @@ -79,27 +79,32 @@ sw $ra, EOFFSET_RA(\r) sw $k1, EOFFSET_K1(\r) - + mfc0 $t0, $status mfc0 $t1, $epc - and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE - li $t3, ~(0x1f) - and $t0, $t0, $t3 # Clear KSU,EXL,ERL,IE - - sw $t2,EOFFSET_STATUS(\r) - sw $t1,EOFFSET_EPC(\r) + # save only KSU, EXL, ERL, IE + and $t2, $t0, REG_SAVE_MASK + + # clear KSU, EXL, ERL, IE + li $t3, ~(REG_SAVE_MASK) + and $t0, $t0, $t3 + + sw $t2, EOFFSET_STATUS(\r) + sw $t1, EOFFSET_EPC(\r) mtc0 $t0, $status .endm .macro REGISTERS_LOAD r - # Update only UM,EXR,IE from status, the rest + # Update only UM, EXR, IE from status, the rest # is controlled by OS and not bound to task mfc0 $t0, $status lw $t1,EOFFSET_STATUS(\r) - - li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE + + # Mask UM, EXL, ERL, IE + li $t2, ~REG_SAVE_MASK and $t0, $t0, $t2 - or $t0, $t0, $t1 # Copy UM,EXL, ERL, IE from saved status + # Copy UM, EXL, ERL, IE from saved status + or $t0, $t0, $t1 mtc0 $t0, $status @@ -129,5 +134,5 @@ lw $at, EOFFSET_HI(\r) mthi $at - + lw $at, EOFFSET_EPC(\r) mtc0 $at, $epc @@ -138,8 +143,7 @@ # Move kernel stack pointer address to register K0 -# - if we are in user mode, load the appropriate stack -# address +# - if we are in user mode, load the appropriate stack address .macro KERNEL_STACK_TO_K0 - # If we are in user mode + # if we are in user mode mfc0 $k0, $status andi $k0, 0x10 @@ -148,24 +152,25 @@ add $k0, $sp, 0 - # Move $k0 pointer to kernel stack + # move $k0 pointer to kernel stack lui $k0, %hi(supervisor_sp) ori $k0, $k0, %lo(supervisor_sp) - # Move $k0 (superveisor_sp) + + # move $k0 (supervisor_sp) lw $k0, 0($k0) -1: + + 1: .endm .org 0x0 kernel_image_start: - /* Load temporary stack */ + # load temporary stack lui $sp, %hi(end_stack) ori $sp, $sp, %lo(end_stack) - /* Not sure about this, but might - be needed for PIC code */ + # Not sure about this, but might + # be needed for PIC code lui $gp, 0x8000 - /* $a1 contains physical address of bootinfo_t */ - + # $a1 contains physical address of bootinfo_t jal arch_pre_main nop @@ -174,5 +179,5 @@ nop - .space TEMP_STACK_SIZE +.space TEMP_STACK_SIZE end_stack: @@ -191,4 +196,5 @@ exception_handler: KERNEL_STACK_TO_K0 + sub $k0, REGISTER_SPACE sw $sp, EOFFSET_SP($k0) @@ -209,5 +215,5 @@ jal exc_dispatch # exc_dispatch(excno, register_space) move $a0, $k0 - + REGISTERS_LOAD $sp # The $sp is automatically restored to former value @@ -276,5 +282,5 @@ eret - + tlb_refill_handler: KERNEL_STACK_TO_K0 Index: kernel/arch/ppc32/include/atomic.h =================================================================== --- kernel/arch/ppc32/include/atomic.h (revision d354d57caee72a5cbe1a16c069ff43d067f07966) +++ kernel/arch/ppc32/include/atomic.h (revision d92bf462a666dbc8e25bc56006b03724997951c4) @@ -42,11 +42,11 @@ asm volatile ( "1:\n" - "lwarx %0, 0, %2\n" - "addic %0, %0, 1\n" - "stwcx. %0, 0, %2\n" - "bne- 1b" - : "=&r" (tmp), + " lwarx %[tmp], 0, %[count_ptr]\n" + " addic %[tmp], %[tmp], 1\n" + " stwcx. %[tmp], 0, %[count_ptr]\n" + " bne- 1b" + : [tmp] "=&r" (tmp), "=m" (val->count) - : "r" (&val->count), + : [count_ptr] "r" (&val->count), "m" (val->count) : "cc" @@ -60,11 +60,11 @@ asm volatile ( "1:\n" - "lwarx %0, 0, %2\n" - "addic %0, %0, -1\n" - "stwcx. %0, 0, %2\n" - "bne- 1b" - : "=&r" (tmp), + " lwarx %[tmp], 0, %[count_ptr]\n" + " addic %[tmp], %[tmp], -1\n" + " stwcx. %[tmp], 0, %[count_ptr]\n" + " bne- 1b" + : [tmp] "=&r" (tmp), "=m" (val->count) - : "r" (&val->count), + : [count_ptr] "r" (&val->count), "m" (val->count) : "cc" Index: kernel/arch/ppc32/include/barrier.h =================================================================== --- kernel/arch/ppc32/include/barrier.h (revision d354d57caee72a5cbe1a16c069ff43d067f07966) +++ kernel/arch/ppc32/include/barrier.h (revision d92bf462a666dbc8e25bc56006b03724997951c4) @@ -27,5 +27,5 @@ */ -/** @addtogroup ppc32 +/** @addtogroup ppc32 * @{ */ @@ -36,10 +36,18 @@ #define KERN_ppc32_BARRIER_H_ -#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") -#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") +#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory") +#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory") -#define memory_barrier() asm volatile ("sync" ::: "memory") -#define read_barrier() asm volatile ("sync" ::: "memory") -#define write_barrier() asm volatile ("eieio" ::: "memory") +#define memory_barrier() asm volatile ("sync" ::: "memory") +#define read_barrier() asm volatile ("sync" ::: "memory") +#define write_barrier() asm volatile ("eieio" ::: "memory") + +#define instruction_barrier() \ + asm volatile ( \ + "sync\n" \ + "isync\n" \ + ) + +#define COHERENCE_INVAL_MIN 4 /* @@ -53,33 +61,32 @@ { asm volatile ( - "dcbst 0, %0\n" + "dcbst 0, %[addr]\n" "sync\n" - "icbi 0, %0\n" + "icbi 0, %[addr]\n" "sync\n" "isync\n" - :: "r" (addr) + :: [addr] "r" (addr) ); } -#define COHERENCE_INVAL_MIN 4 - -static inline void smc_coherence_block(void *addr, unsigned long len) +static inline void smc_coherence_block(void *addr, unsigned int len) { - unsigned long i; - - for (i = 0; i < len; i += COHERENCE_INVAL_MIN) { - asm volatile ("dcbst 0, %0\n" :: "r" (addr + i)); - } - - asm volatile ("sync"); - - for (i = 0; i < len; i += COHERENCE_INVAL_MIN) { - asm volatile ("icbi 0, %0\n" :: "r" (addr + i)); - } - - asm volatile ( - "sync\n" - "isync\n" - ); + unsigned int i; + + for (i = 0; i < len; i += COHERENCE_INVAL_MIN) + asm volatile ( + "dcbst 0, %[addr]\n" + :: [addr] "r" (addr + i) + ); + + memory_barrier(); + + for (i = 0; i < len; i += COHERENCE_INVAL_MIN) + asm volatile ( + "icbi 0, %[addr]\n" + :: [addr] "r" (addr + i) + ); + + instruction_barrier(); } Index: kernel/arch/ppc32/include/cycle.h =================================================================== --- kernel/arch/ppc32/include/cycle.h (revision d354d57caee72a5cbe1a16c069ff43d067f07966) +++ kernel/arch/ppc32/include/cycle.h (revision d92bf462a666dbc8e25bc56006b03724997951c4) @@ -40,17 +40,16 @@ uint32_t lower; uint32_t upper; - uint32_t upper2; + uint32_t tmp; - asm volatile ( - "1: mftbu %0\n" - "mftb %1\n" - "mftbu %2\n" - "cmpw %0, %2\n" - "bne- 1b\n" - : "=r" (upper), - "=r" (lower), - "=r" (upper2) - :: "cr0" - ); + do { + asm volatile ( + "mftbu %[upper]\n" + "mftb %[lower]\n" + "mftbu %[tmp]\n" + : [upper] "=r" (upper), + [lower] "=r" (lower), + [tmp] "=r" (tmp) + ); + } while (upper != tmp); return ((uint64_t) upper << 32) + (uint64_t) lower; Index: kernel/arch/ppc32/src/proc/scheduler.c =================================================================== --- kernel/arch/ppc32/src/proc/scheduler.c (revision d354d57caee72a5cbe1a16c069ff43d067f07966) +++ kernel/arch/ppc32/src/proc/scheduler.c (revision d92bf462a666dbc8e25bc56006b03724997951c4) @@ -39,17 +39,21 @@ #include -/** Perform ppc32 specific tasks needed before the new task is run. */ +/** Perform ppc32 specific tasks needed before the new task is run. + * + */ void before_task_runs_arch(void) { } -/** Perform ppc32 specific tasks needed before the new thread is scheduled. */ +/** Perform ppc32 specific tasks needed before the new thread is scheduled. + * + */ void before_thread_runs_arch(void) { tlb_invalidate_all(); + asm volatile ( - "mtsprg0 %0\n" - : - : "r" (KA2PA(&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA])) + "mtsprg0 %[ksp]\n" + :: [ksp] "r" (KA2PA(&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA])) ); }