Changeset d6e5cbc in mainline for arch/mips32/src


Ignore:
Timestamp:
2006-05-28T18:17:36Z (19 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5552d60
Parents:
3bf5976
Message:

Added 'realtime' clock interface.
Added some asm macros as memory barriers.
Added drift computing for mips platform.

Location:
arch/mips32/src
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • arch/mips32/src/interrupt.c

    r3bf5976 rd6e5cbc  
    7777}
    7878
     79/* TODO: This is SMP unsafe!!! */
     80static unsigned long nextcount;
     81/** Start hardware clock */
     82static void timer_start(void)
     83{
     84        nextcount = cp0_compare_value + cp0_count_read();
     85        cp0_compare_write(nextcount);
     86}
     87
    7988static void timer_exception(int n, istate_t *istate)
    8089{
    81         cp0_compare_write(cp0_count_read() + cp0_compare_value);
     90        unsigned long drift;
     91
     92        drift = cp0_count_read() - nextcount;
     93        while (drift > cp0_compare_value) {
     94                drift -= cp0_compare_value;
     95                CPU->missed_clock_ticks++;
     96        }
     97        nextcount = cp0_count_read() + cp0_compare_value - drift;
     98        cp0_compare_write(nextcount);
    8299        clock();
    83100}
     
    101118        int_register(0, "swint0", swint0);
    102119        int_register(1, "swint1", swint1);
     120        timer_start();
    103121}
    104122
  • arch/mips32/src/mips32.c

    r3bf5976 rd6e5cbc  
    8181        /* Initialize dispatch table */
    8282        exception_init();
    83         interrupt_init();
    84 
    8583        arc_init();
    8684
     
    9088        memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
    9189
     90        interrupt_init();
    9291        /*
    9392         * Switch to BEV normal level so that exception vectors point to the kernel.
     
    10099         */
    101100        cp0_mask_all_int();
     101
    102102        /*
    103103         * Unmask hardware clock interrupt.
    104104         */
    105105        cp0_unmask_int(TIMER_IRQ);
    106 
    107         /*
    108          * Start hardware clock.
    109          */
    110         cp0_compare_write(cp0_compare_value + cp0_count_read());
    111106
    112107        console_init();
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