Changeset d6e5cbc in mainline for arch/mips32/include


Ignore:
Timestamp:
2006-05-28T18:17:36Z (20 years ago)
Author:
Ondrej Palkovsky <ondrap@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5552d60
Parents:
3bf5976
Message:

Added 'realtime' clock interface.
Added some asm macros as memory barriers.
Added drift computing for mips platform.

Location:
arch/mips32/include
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • arch/mips32/include/barrier.h

    r3bf5976 rd6e5cbc  
    3636#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    3737
    38 #define memory_barrier()
    39 #define read_barrier()
    40 #define write_barrier()
     38#define memory_barrier()        __asm__ volatile ("" ::: "memory")
     39#define read_barrier()          __asm__ volatile ("" ::: "memory")
     40#define write_barrier()         __asm__ volatile ("" ::: "memory")
    4141
    4242#endif

  • arch/mips32/include/cp0.h

    r3bf5976 rd6e5cbc  
    5050/*
    5151 * Magic value for use in msim.
    52  * On AMD Duron 800Mhz, this roughly seems like one us.
    5352 */
    54 #define cp0_compare_value               10000
     53#define cp0_compare_value               100000
    5554
    5655#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
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