Changeset ce031f0 in mainline for arch/mips32/include/mm/tlb.h
- Timestamp:
- 2005-10-04T11:23:21Z (20 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8e3f47b3
- Parents:
- 1e2aecca
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/mips32/include/mm/tlb.h
r1e2aecca rce031f0 31 31 32 32 #include <arch/exception.h> 33 34 #define TLB_SIZE 48 35 36 #define TLB_WIRED 1 37 #define TLB_KSTACK_WIRED_INDEX 0 38 39 #define TLB_PAGE_MASK_16K (0x3<<13) 33 40 34 41 #define PAGE_UNCACHED 2 … … 66 73 typedef struct entry_lo pte_t; 67 74 75 /** Read Indexed TLB Entry 76 * 77 * Read Indexed TLB Entry. 78 */ 79 static inline void tlbr(void) 80 { 81 __asm__ volatile ("tlbr\n\t"); 82 } 83 84 /** Write Indexed TLB Entry 85 * 86 * Write Indexed TLB Entry. 87 */ 88 static inline void tlbwi(void) 89 { 90 __asm__ volatile ("tlbwi\n\t"); 91 } 92 93 /** Write Random TLB Entry 94 * 95 * Write Random TLB Entry. 96 */ 97 static inline void tlbwr(void) 98 { 99 __asm__ volatile ("tlbwr\n\t"); 100 } 101 68 102 extern void tlb_invalid(struct exception_regdump *pstate); 69 103 extern void tlb_refill(struct exception_regdump *pstate); 104 extern void tlb_modified(struct exception_regdump *pstate); 70 105 71 106 #endif
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