Changeset cb89430 in mainline for uspace/drv/bus/usb/xhci/hw_struct


Ignore:
Timestamp:
2017-06-22T13:59:15Z (8 years ago)
Author:
Ondřej Hlavatý <aearsis@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
e4d7363
Parents:
62ba2cbe
Message:

xhci: event rings && hc initialization (WIP)

Location:
uspace/drv/bus/usb/xhci/hw_struct
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/bus/usb/xhci/hw_struct/context.h

    r62ba2cbe rcb89430  
    4343
    4444#include <stdint.h>
    45 #include <common.h>
     45#include "common.h"
    4646
    4747/**
    … …  
    6767#define XHCI_EP_TR_DPTR(ctx)            XHCI_DWORD_EXTRACT((ctx).data[2], 63,  4)
    6868
    69 } ep_ctx_t __attribute__((packed));
     69} __attribute__((packed)) xhci_ep_ctx_t;
    7070
    7171/**
    … …  
    9393#define XHCI_SLOT_SLOT_STATE(ctx)       XHCI_DWORD_EXTRACT((ctx).data[3], 31, 27)
    9494
    95 } xhci_slot_ctx_t __attribute__((packed));
     95} __attribute__((packed)) xhci_slot_ctx_t;
    9696
    9797/**
    … …  
    101101        xhci_slot_ctx_t slot_ctx;
    102102        xhci_ep_ctx_t endpoint_ctx [31];
    103 } xhci_device_ctx_t;
     103} __attribute__((packed)) xhci_device_ctx_t;
    104104
    105105/**
    … …  
    108108typedef struct xhci_stream_ctx {
    109109        uint64_t data [2];
    110 } xhci_stream_ctx_t __attribute__((packed));
     110} __attribute__((packed)) xhci_stream_ctx_t;
    111111
    112112#endif

  • uspace/drv/bus/usb/xhci/hw_struct/regs.h

    r62ba2cbe rcb89430  
    4343#include "common.h"
    4444
    45 /*
    46  */
    47 
    4845#define XHCI_PIO_CHANGE_UDELAY 5
    49 
    50 #define host2xhci(size, val) host2uint##size##_t_le((val))
    51 #define xhci2host(size, val) uint##size##_t_le2host((val))
    5246
    5347/*
    … …  
    6357#define XHCI_REG_SET(reg_set, reg_spec, value) XHCI_REG_SET_INNER(reg_set, value, reg_spec)
    6458#define XHCI_REG_CLR(reg_set, reg_spec, value) XHCI_REG_CLR_INNER(reg_set, value, reg_spec)
     59#define XHCI_REG_MASK(reg_spec)                XHCI_REG_MASK_INNER(reg_spec)
     60#define XHCI_REG_SHIFT(reg_spec)               XHCI_REG_SHIFT_INNER(reg_spec)
    6561
    6662/*
    … …  
    7874#define XHCI_REG_CLR_INNER(reg_set, value, field, size, type, ...) \
    7975        XHCI_REG_CLR_##type(&(reg_set)->field, value, size, ##__VA_ARGS__)
     76
     77#define XHCI_REG_MASK_INNER(field, size, type, ...) \
     78        XHCI_REG_MASK_##type(size, ##__VA_ARGS__)
     79
     80#define XHCI_REG_SHIFT_INNER(field, size, type, ...) \
     81        XHCI_REG_SHIFT_##type(size, ##__VA_ARGS__)
    8082
    8183/*
    … …  
    8688#define XHCI_REG_SET_FIELD(ptr, value, size) pio_set_##size((ptr), host2xhci(size, value), XHCI_PIO_CHANGE_UDELAY);
    8789#define XHCI_REG_CLR_FIELD(ptr, value, size) pio_clear_##size((ptr), host2xhci(size, value), XHCI_PIO_CHANGE_UDELAY);
     90#define XHCI_REG_MASK_FIELD(size)            (~((uint##size##_t) 0))
     91#define XHCI_REG_SHIFT_FIELD(size)           (0)
    8892
    8993/*
    … …  
    9498#define XHCI_REG_SET_FLAG(ptr, value, size, offset) XHCI_REG_SET_RANGE((ptr), (value), size, (offset), (offset))
    9599#define XHCI_REG_CLR_FLAG(ptr, value, size, offset) XHCI_REG_CLR_RANGE((ptr), (value), size, (offset), (offset))
     100#define XHCI_REG_MASK_FLAG(size, offset)            BIT_V(uint##size##_t, offset)
     101#define XHCI_REG_SHIFT_FLAG(size, offset)           (offset)
    96102
    97103/*
    … …  
    113119        pio_clear_##size((ptr), host2xhci(size, BIT_RANGE_INSERT(uint##size##_t, (hi), (lo), (value))), \
    114120                XHCI_PIO_CHANGE_UDELAY);
     121
     122#define XHCI_REG_MASK_RANGE(size, hi, lo)  BIT_RANGE(uint##size##_t, hi, lo)
     123#define XHCI_REG_SHIFT_RANGE(size, hi, lo) (lo)
    115124
    116125/** HC capability registers: section 5.3 */
    … …  
    215224#define XHCI_CAP_CIC          hccparams2, 32,  FLAG,  5
    216225
     226static inline unsigned xhci_get_max_spbuf(xhci_cap_regs_t *cap_regs) {
     227        return XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_HI) << 5
     228                | XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_LO);
     229}
     230
    217231/**
    218232 * XHCI Port Register Set: section 5.4, table 32
    … …  
    395409#define XHCI_OP_CRCR_LO        crcr_lo, 32, RANGE, 31, 6
    396410#define XHCI_OP_CRCR_HI        crcr_lo, 32, FIELD
     411#define XHCI_OP_DCBAAP_LO    dcbaap_lo, 32, FIELD
     412#define XHCI_OP_DCBAAP_HI    dcbaap_lo, 32, FIELD
     413#define XHCI_OP_MAX_SLOTS_EN    config, 32, RANGE, 7, 0
     414#define XHCI_OP_U3E             config, 32,  FLAG, 8
     415#define XHCI_OP_CIE             config, 32,  FLAG, 9
     416
     417/* Aggregating field to read & write whole status at once */
     418#define XHCI_OP_STATUS          usbsts, 32, RANGE, 12, 0
     419
     420/* RW1C fields in usbsts */
     421#define XHCI_STATUS_ACK_MASK     0x41C
    397422
    398423/**
    … …  
    444469        ioport32_t mfindex;
    445470
    446         PADD32 [5];
    447 
    448         xhci_interrupter_regs_t ir[1024];
     471        PADD32 [7];
     472
     473        xhci_interrupter_regs_t ir [];
    449474} xhci_rt_regs_t;
    450475
    … …  
    452477
    453478/**
    454  * XHCI Doorbel Registers: section 5.6
    455  *
    456  * These registers are write-only, thus convenience macros are useless.
     479 * XHCI Doorbell Registers: section 5.6
     480 *
     481 * These registers are to be written as a whole field.
    457482 */
    458483typedef ioport32_t xhci_doorbell_t;

  • uspace/drv/bus/usb/xhci/hw_struct/trb.h

    r62ba2cbe rcb89430  
    8484        XHCI_TRB_TYPE_DEVICE_NOTIFICATION_EVENT,
    8585        XHCI_TRB_TYPE_MFINDEX_WRAP_EVENT,
     86
     87        XHCI_TRB_TYPE_MAX
    8688};
    8789
    … …  
    9395        xhci_dword_t status;
    9496        xhci_dword_t control;
    95 } xhci_trb_t;
     97} __attribute__((packed)) xhci_trb_t;
    9698
    9799#define TRB_TYPE(trb)           XHCI_DWORD_EXTRACT((trb).control, 15, 10)
     100#define TRB_CYCLE(trb)          XHCI_DWORD_EXTRACT((trb).control, 0, 0)
    98101#define TRB_LINK_TC(trb)        XHCI_DWORD_EXTRACT((trb).control, 1, 1)
    99102
    … …  
    114117static inline void xhci_trb_set_cycle(xhci_trb_t *trb, bool cycle)
    115118{
    116         xhci_dword_set_bits(&trb->control, cycle, 1, 1);
     119        xhci_dword_set_bits(&trb->control, cycle, 0, 0);
    117120}
    118121
    … …  
    137140}
    138141
    139 
    140142/**
    141143 * Event Ring Segment Table: section 6.5
    142144 */
    143145typedef struct xhci_erst_entry {
    144         xhci_qword_t rs_base_ptr;       // sans bits 0-6
    145         xhci_dword_t size;              // only low 16 bits, the rest is reserved
     146        xhci_qword_t rs_base_ptr;       /* 64B aligned */
     147        xhci_dword_t size;              /* only low 16 bits, the rest is RsvdZ */
     148        xhci_dword_t _reserved;
    146149} xhci_erst_entry_t;
    147150
     151static inline void xhci_fill_erst_entry(xhci_erst_entry_t *entry, uintptr_t phys, int segments)
     152{
     153        xhci_qword_set(&entry->rs_base_ptr, phys);
     154        xhci_dword_set_bits(&entry->size, segments, 16, 0);
     155}
     156
    148157#endif
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