Changeset ca62f86 in mainline for kernel/genarch

Timestamp:

2013-09-09T17:52:40Z (12 years ago)

Author:

Jakub Klama <jakub.klama@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f7bb6d1

Parents:

6ad185d (diff), a1ecb88 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

Location:

kernel/genarch

Files:

• include/genarch/drivers/amdm37x/gpt.h (modified) (5 diffs)
• src/mm/page_pt.c (modified) (2 diffs)

kernel/genarch/include/genarch/drivers/amdm37x/gpt.h

@@ -39 +39 @@
 #include <typedefs.h>
 #include <mm/km.h>
+#include <time/clock.h>
 
 /* AMDM37x TRM p. 2740 */
@@ -128 +129 @@
 #define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
 #define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
-#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
-#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
+#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3 << 8)
+#define AMDM37x_GPT_TCLR_TCM_NO_CAPTURE   (0x0 << 8)
+#define AMDM37x_GPT_TCLR_TCM_RAISE_CAPTURE   (0x1 << 8)
+#define AMDM37x_GPT_TCLR_TCM_FALL_CAPTURE   (0x2 << 8)
+#define AMDM37x_GPT_TCLR_TCM_BOTH_CAPTURE   (0x3 << 8)
+#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3 << 10)
+#define AMDM37x_GPT_TCLR_TRG_NO  (0x0 << 10)
+#define AMDM37x_GPT_TCLR_TRG_OVERFLOW  (0x1 << 10)
+#define AMDM37x_GPT_TCLR_TRG_OVERMATCH  (0x2 << 10)
 #define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
 #define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
@@ -209 +215 @@
         timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
 
+        /* Reset the timer */
+        timer->regs->tiocp_cfg |= AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG;
+
+        while (!(timer->regs->tistat & AMDM37x_GPT_TISTAT_RESET_DONE_FLAG));
+
         /* Set autoreload */
-        timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
+        timer->regs->tclr |= AMDM37x_GPT_TCLR_AR_FLAG;
 
         timer->special_available = (
@@ -216 +227 @@
             (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
             (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
+        /* Select reload value */
         timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
+        /* Set current counter value */
         timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
+
         if (timer->special_available) {
-                /* Set values for according to formula (manual p. 2733) */
+                /* Set values according to formula (manual p. 2733) */
                 /* Use temporary variables for easier debugging */
                 const uint32_t tpir =
                     ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
                 const uint32_t tnir =
-                    ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
+                    ((32768 / hz) * 1000000) - (32768000L * (1000 / hz));
                 timer->regs->tpir = tpir;
                 timer->regs->tnir = tnir;
@@ -241 +255 @@
 }
 
-static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
+static inline bool amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
 {
         ASSERT(timer);
         ASSERT(timer->regs);
         /* Clear all pending interrupts */
-        timer->regs->tisr = timer->regs->tisr;
+        const uint32_t tisr = timer->regs->tisr;
+        timer->regs->tisr = tisr;
+        return tisr != 0;
 }
 

kernel/genarch/src/mm/page_pt.c

@@ -112 +112 @@
                  */
                 write_barrier();
-                SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page));       
+                SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page));
         }
         
@@ -180 +180 @@
          * Destroy the mapping.
          * Setting to PAGE_NOT_PRESENT is not sufficient.
-         */
+         * But we need SET_FRAME for possible PT coherence maintenance.
+         * At least on ARM.
+         */
+        //TODO: Fix this inconsistency
+        SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), PAGE_NOT_PRESENT);
         memsetb(&ptl3[PTL3_INDEX(page)], sizeof(pte_t), 0);