Changeset c9b8c5c in mainline for arch/ia32/include


Ignore:
Timestamp:
2005-04-24T21:59:33Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
ad36bd6
Parents:
f07bba5
Message:

APIC changes and fixes.
Be more robust during MP configuration.

Do not use APIC ID as CPU_ID_ARCH anymore.
Changing APIC ID's is not a good idea.
Use dr0 register instead.

Location:
arch/ia32/include
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • arch/ia32/include/asm.h

    rf07bba5 rc9b8c5c  
    5959extern void cpu_sleep(void);
    6060
     61extern void write_dr0(__u32 v);
     62extern __u32 read_dr0(void);
     63
    6164#endif

  • arch/ia32/include/cpu.h

    rf07bba5 rc9b8c5c  
    3535
    3636#ifdef __SMP__
    37 #define CPU_ID_ARCH     ((config.cpu_active>1)?l_apic_id():0)
     37#define CPU_ID_ARCH     (read_dr0())
    3838#else
    3939#define CPU_ID_ARCH     (0)

  • arch/ia32/include/smp/apic.h

    rf07bba5 rc9b8c5c  
    9999#define L_APIC_IDMask   0xf
    100100
     101/* Local APIC Version Register */
     102#define LAVR            (0x030/sizeof(__u32))
     103#define LAVR_Mask       0xff
     104#define is_local_apic(x)        (((x)&LAVR_Mask&0xf0)==0x1)
     105#define is_82489DX_apic(x)      ((((x)&LAVR_Mask&0xf0)==0x0))
     106#define is_local_xapic(x)       (((x)&LAVR_Mask)==0x14)
     107
    101108/* IO APIC */
    102109#define IOREGSEL        (0x00/sizeof(__u32))
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