Index: .bzrignore =================================================================== --- .bzrignore (revision c2a698383608df44fde7e7cb4047a416d8688eee) +++ .bzrignore (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -0,0 +1,280 @@ +*.disasm +*.map +*.prev +Makefile.depend +Makefile.common +Makefile.config +cscope.out +autotool/ +common.h +config.h +hdisk.img +image.iso +boot/distroot/ +boot/initrd.img +kernel/kernel.bin +kernel/kernel.dump +kernel/kernel.raw +kernel/arch/amd64/_link.ld +kernel/arch/amd64/include/arch/common.h +kernel/generic/src/debug/real_map.bin +uspace/app/bdsh/bdsh +uspace/app/bithenge/bithenge +uspace/app/blkdump/blkdump +uspace/app/bnchmark/bnchmark +uspace/app/date/date +uspace/app/devctl/devctl +uspace/app/dnscfg/dnscfg +uspace/app/dnsres/dnsres +uspace/app/edit/edit +uspace/app/getterm/getterm +uspace/app/inet/inet +uspace/app/init/init +uspace/app/kill/kill +uspace/app/killall/killall +uspace/app/klog/klog +uspace/app/loc/loc +uspace/app/logset/logset +uspace/app/mixerctl/mixerctl +uspace/app/mkbd/mkbd +uspace/app/mkexfat/mkexfat +uspace/app/mkfat/mkfat +uspace/app/mkmfs/mkmfs +uspace/app/netecho/netecho +uspace/app/nettest1/nettest1 +uspace/app/nettest2/nettest2 +uspace/app/nettest3/nettest3 +uspace/app/nterm/nterm +uspace/app/ping/ping +uspace/app/ping6/ping6 +uspace/app/redir/redir +uspace/app/sbi/sbi +uspace/app/sportdmp/sportdmp +uspace/app/stats/stats +uspace/app/sysinfo/sysinfo +uspace/app/taskdump/taskdump +uspace/app/tester/tester +uspace/app/testread/testread +uspace/app/testwrit/testwrit +uspace/app/tetris/tetris +uspace/app/top/top +uspace/app/trace/trace +uspace/app/usbinfo/usbinfo +uspace/app/vdemo/vdemo +uspace/app/vlaunch/images.c +uspace/app/vlaunch/images.h +uspace/app/vlaunch/vlaunch +uspace/app/vterm/vterm +uspace/app/vuhid/vuh +uspace/app/wavplay/wavplay +uspace/app/websrv/websrv +uspace/dist/app/bdsh +uspace/dist/app/bithenge +uspace/dist/app/blkdump +uspace/dist/app/bnchmark +uspace/dist/app/date +uspace/dist/app/devctl +uspace/dist/app/dnscfg +uspace/dist/app/dnsres +uspace/dist/app/edit +uspace/dist/app/getterm +uspace/dist/app/inet +uspace/dist/app/kill +uspace/dist/app/killall +uspace/dist/app/klog +uspace/dist/app/loc +uspace/dist/app/logset +uspace/dist/app/mixerctl +uspace/dist/app/mkbd +uspace/dist/app/mkexfat +uspace/dist/app/mkfat +uspace/dist/app/mkmfs +uspace/dist/app/netecho +uspace/dist/app/nettest1 +uspace/dist/app/nettest2 +uspace/dist/app/nettest3 +uspace/dist/app/nterm +uspace/dist/app/ping +uspace/dist/app/ping6 +uspace/dist/app/redir +uspace/dist/app/sbi +uspace/dist/app/sportdmp +uspace/dist/app/stats +uspace/dist/app/sysinfo +uspace/dist/app/taskdump +uspace/dist/app/tester +uspace/dist/app/testread +uspace/dist/app/testwrit +uspace/dist/app/tetris +uspace/dist/app/top +uspace/dist/app/trace +uspace/dist/app/usbinfo +uspace/dist/app/vdemo +uspace/dist/app/vlaunch +uspace/dist/app/vterm +uspace/dist/app/vuh +uspace/dist/app/wavplay +uspace/dist/app/websrv +uspace/dist/drv/ahci/ +uspace/dist/drv/ata_bd/ +uspace/dist/drv/cmos-rtc/ +uspace/dist/drv/e1k/ +uspace/dist/drv/ehci/ +uspace/dist/drv/i8042/ +uspace/dist/drv/isa/ +uspace/dist/drv/kfb/ +uspace/dist/drv/ne2k/ +uspace/dist/drv/ns8250/ +uspace/dist/drv/ohci/ +uspace/dist/drv/pciintel/ +uspace/dist/drv/ps2mouse/ +uspace/dist/drv/root/ +uspace/dist/drv/rootpc/ +uspace/dist/drv/rootvirt/ +uspace/dist/drv/rtl8139/ +uspace/dist/drv/sb16/ +uspace/dist/drv/test1/ +uspace/dist/drv/test2/ +uspace/dist/drv/test3/ +uspace/dist/drv/uhci/ +uspace/dist/drv/uhcirh/ +uspace/dist/drv/usbflbk/ +uspace/dist/drv/usbhid/ +uspace/dist/drv/usbhub/ +uspace/dist/drv/usbmast/ +uspace/dist/drv/usbmid/ +uspace/dist/drv/vhc/ +uspace/dist/drv/xtkbd/ +uspace/dist/srv/apic +uspace/dist/srv/cdfs +uspace/dist/srv/clipboard +uspace/dist/srv/compositor +uspace/dist/srv/console +uspace/dist/srv/devman +uspace/dist/srv/dnsrsrv +uspace/dist/srv/ethip +uspace/dist/srv/exfat +uspace/dist/srv/ext4fs +uspace/dist/srv/fat +uspace/dist/srv/file_bd +uspace/dist/srv/g_part +uspace/dist/srv/hound +uspace/dist/srv/i8259 +uspace/dist/srv/inetsrv +uspace/dist/srv/input +uspace/dist/srv/isdv4_tablet +uspace/dist/srv/locfs +uspace/dist/srv/loopip +uspace/dist/srv/mbr_part +uspace/dist/srv/mfs +uspace/dist/srv/output +uspace/dist/srv/remcons +uspace/dist/srv/sata_bd +uspace/dist/srv/slip +uspace/dist/srv/taskmon +uspace/dist/srv/tcp +uspace/dist/srv/tmpfs +uspace/dist/srv/udf +uspace/dist/srv/udp +uspace/drv/audio/sb16/sb16 +uspace/drv/block/ahci/ahci +uspace/drv/block/ata_bd/ata_bd +uspace/drv/bus/isa/isa +uspace/drv/bus/pci/pciintel/pciintel +uspace/drv/bus/usb/ehci/ehci +uspace/drv/bus/usb/ohci/ohci +uspace/drv/bus/usb/uhci/uhci +uspace/drv/bus/usb/uhcirh/uhcirh +uspace/drv/bus/usb/usbflbk/usbflbk +uspace/drv/bus/usb/usbhid/usbhid +uspace/drv/bus/usb/usbhub/usbhub +uspace/drv/bus/usb/usbmast/usbmast +uspace/drv/bus/usb/usbmid/usbmid +uspace/drv/bus/usb/vhc/vhc +uspace/drv/char/i8042/i8042 +uspace/drv/char/ns8250/ns8250 +uspace/drv/char/ps2mouse/ps2mouse +uspace/drv/char/xtkbd/xtkbd +uspace/drv/fb/kfb/kfb +uspace/drv/infrastructure/root/root +uspace/drv/infrastructure/rootpc/rootpc +uspace/drv/infrastructure/rootvirt/rootvirt +uspace/drv/nic/e1k/e1k +uspace/drv/nic/ne2k/ne2k +uspace/drv/nic/rtl8139/rtl8139 +uspace/drv/test/test1/test1 +uspace/drv/test/test2/test2 +uspace/drv/test/test3/test3 +uspace/drv/time/cmos-rtc/cmos-rtc +uspace/lib/c/arch/amd64/_link-dlexe.ld +uspace/lib/c/arch/amd64/_link-loader.ld +uspace/lib/c/arch/amd64/_link-shlib.ld +uspace/lib/c/arch/amd64/_link.ld +uspace/lib/c/arch/amd64/include/libarch/common.h +uspace/lib/posix/collisions.list +uspace/lib/posix/redefs-hide-libc.xargs +uspace/lib/posix/redefs-show-posix.xargs +uspace/lib/posix/include/libc +uspace/srv/audio/hound/hound +uspace/srv/bd/file_bd/file_bd +uspace/srv/bd/part/guid_part/g_part +uspace/srv/bd/part/mbr_part/mbr_part +uspace/srv/bd/rd/rd +uspace/srv/bd/sata_bd/sata_bd +uspace/srv/clipboard/clipboard +uspace/srv/devman/devman +uspace/srv/fs/cdfs/cdfs +uspace/srv/fs/exfat/exfat +uspace/srv/fs/ext4fs/ext4fs +uspace/srv/fs/fat/fat +uspace/srv/fs/locfs/locfs +uspace/srv/fs/mfs/mfs +uspace/srv/fs/tmpfs/tmpfs +uspace/srv/fs/udf/udf +uspace/srv/hid/compositor/compositor +uspace/srv/hid/compositor/images.c +uspace/srv/hid/compositor/images.h +uspace/srv/hid/console/console +uspace/srv/hid/input/input +uspace/srv/hid/isdv4_tablet/isdv4_tablet +uspace/srv/hid/output/output +uspace/srv/hid/remcons/remcons +uspace/srv/hid/s3c24xx_ts/s3c24xx_ts +uspace/srv/hw/char/s3c24xx_uart/s3c24ser +uspace/srv/hw/irc/apic/apic +uspace/srv/hw/irc/i8259/i8259 +uspace/srv/loader/loader +uspace/srv/locsrv/locsrv +uspace/srv/logger/logger +uspace/srv/net/dnsrsrv/dnsrsrv +uspace/srv/net/ethip/ethip +uspace/srv/net/inetsrv/inetsrv +uspace/srv/net/loopip/loopip +uspace/srv/net/slip/slip +uspace/srv/net/tcp/tcp +uspace/srv/net/udp/udp +uspace/srv/ns/ns +uspace/srv/taskmon/taskmon +uspace/srv/vfs/vfs +kernel/arch/ia32/_link.ld +uspace/lib/c/arch/ia32/_link-dlexe.ld +uspace/lib/c/arch/ia32/_link-loader.ld +uspace/lib/c/arch/ia32/_link-shlib.ld +uspace/lib/c/arch/ia32/_link.ld +kernel/arch/arm32/_link.ld +uspace/app/corecfg/corecfg +uspace/dist/app/corecfg +uspace/dist/srv/rfb +uspace/srv/hid/rfb/rfb +uspace/dist/srv/dhcp +uspace/srv/net/dhcp/dhcp +uspace/dist/srv/nconfsrv +uspace/srv/net/nconfsrv/nconfsrv +uspace/app/netspeed/netspeed +uspace/dist/app/netspeed +uspace/app/df/df +uspace/dist/app/df +uspace/app/download/download +uspace/dist/app/download +uspace/app/viewer/viewer +uspace/dist/app/viewer Index: abi/include/abi/ipc/ipc.h =================================================================== --- abi/include/abi/ipc/ipc.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ abi/include/abi/ipc/ipc.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -59,4 +59,10 @@ /** Interrupt notification */ #define IPC_CALL_NOTIF (1 << 3) + +/** + * Maximum buffer size allowed for IPC_M_DATA_WRITE and + * IPC_M_DATA_READ requests. + */ +#define DATA_XFER_LIMIT (64 * 1024) Index: boot/Makefile.common =================================================================== --- boot/Makefile.common (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/Makefile.common (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -112,8 +112,11 @@ $(USPACE_PATH)/srv/hid/remcons/remcons \ $(USPACE_PATH)/srv/hid/isdv4_tablet/isdv4_tablet \ + $(USPACE_PATH)/srv/hid/rfb/rfb \ + $(USPACE_PATH)/srv/net/dhcp/dhcp \ $(USPACE_PATH)/srv/net/dnsrsrv/dnsrsrv \ $(USPACE_PATH)/srv/net/ethip/ethip \ $(USPACE_PATH)/srv/net/inetsrv/inetsrv \ $(USPACE_PATH)/srv/net/loopip/loopip \ + $(USPACE_PATH)/srv/net/nconfsrv/nconfsrv \ $(USPACE_PATH)/srv/net/slip/slip \ $(USPACE_PATH)/srv/net/tcp/tcp \ @@ -121,6 +124,8 @@ $(USPACE_PATH)/srv/taskmon/taskmon -RD_DRVS = \ - infrastructure/root \ +RD_DRVS_ESSENTIAL = \ + infrastructure/root + +RD_DRVS_NON_ESSENTIAL = \ infrastructure/rootvirt \ fb/kfb \ @@ -163,4 +168,5 @@ $(USPACE_PATH)/app/blkdump/blkdump \ $(USPACE_PATH)/app/bnchmark/bnchmark \ + $(USPACE_PATH)/app/corecfg/corecfg \ $(USPACE_PATH)/app/devctl/devctl \ $(USPACE_PATH)/app/dltest/dltest \ @@ -169,4 +175,5 @@ $(USPACE_PATH)/app/dnscfg/dnscfg \ $(USPACE_PATH)/app/dnsres/dnsres \ + $(USPACE_PATH)/app/download/download \ $(USPACE_PATH)/app/edit/edit \ $(USPACE_PATH)/app/inet/inet \ @@ -174,4 +181,5 @@ $(USPACE_PATH)/app/killall/killall \ $(USPACE_PATH)/app/loc/loc \ + $(USPACE_PATH)/app/mixerctl/mixerctl \ $(USPACE_PATH)/app/logset/logset \ $(USPACE_PATH)/app/mkfat/mkfat \ @@ -191,7 +199,7 @@ $(USPACE_PATH)/app/nettest3/nettest3 \ $(USPACE_PATH)/app/netecho/netecho \ + $(USPACE_PATH)/app/netspeed/netspeed \ $(USPACE_PATH)/app/nterm/nterm \ $(USPACE_PATH)/app/ping/ping \ - $(USPACE_PATH)/app/ping6/ping6 \ $(USPACE_PATH)/app/stats/stats \ $(USPACE_PATH)/app/sysinfo/sysinfo \ @@ -202,5 +210,7 @@ $(USPACE_PATH)/app/websrv/websrv \ $(USPACE_PATH)/app/date/date \ - $(USPACE_PATH)/app/vdemo/vdemo + $(USPACE_PATH)/app/vdemo/vdemo \ + $(USPACE_PATH)/app/viewer/viewer \ + $(USPACE_PATH)/app/df/df ifeq ($(CONFIG_PCC),y) @@ -237,7 +247,9 @@ RD_SRVS = $(RD_SRVS_ESSENTIAL) RD_APPS = $(RD_APPS_ESSENTIAL) +RD_DRVS = $(RD_DRVS_ESSENTIAL) else RD_SRVS = $(RD_SRVS_ESSENTIAL) $(RD_SRVS_NON_ESSENTIAL) RD_APPS = $(RD_APPS_ESSENTIAL) $(RD_APPS_NON_ESSENTIAL) +RD_DRVS = $(RD_DRVS_ESSENTIAL) $(RD_DRVS_NON_ESSENTIAL) endif Index: boot/arch/amd64/Makefile.inc =================================================================== --- boot/arch/amd64/Makefile.inc (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/amd64/Makefile.inc (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -28,16 +28,22 @@ RD_SRVS_ESSENTIAL += \ + $(USPACE_PATH)/srv/audio/hound/hound \ + $(USPACE_PATH)/srv/devman/devman \ $(USPACE_PATH)/srv/hw/irc/apic/apic \ $(USPACE_PATH)/srv/hw/irc/i8259/i8259 -RD_DRVS += \ + +RD_DRVS_ESSENTIAL += \ infrastructure/rootpc \ block/ata_bd \ bus/pci/pciintel \ bus/isa \ + audio/sb16 \ char/i8042 \ + char/ps2mouse \ + char/xtkbd + +RD_DRVS_NON_ESSENTIAL += \ char/ns8250 \ - char/ps2mouse \ - char/xtkbd \ time/cmos-rtc \ bus/usb/ehci\ @@ -55,4 +61,9 @@ bus/isa +RD_APPS_ESSENTIAL += \ + $(USPACE_PATH)/app/edit/edit \ + $(USPACE_PATH)/app/mixerctl/mixerctl \ + $(USPACE_PATH)/app/wavplay/wavplay \ + BOOT_OUTPUT = $(ROOT_PATH)/image.iso PREBUILD = $(INITRD).img Index: boot/arch/arm32/Makefile.inc =================================================================== --- boot/arch/arm32/Makefile.inc (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/arm32/Makefile.inc (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -57,5 +57,5 @@ endif -RD_DRVS += \ +RD_DRVS_ESSENTIAL += \ infrastructure/rootamdm37x \ fb/amdm37x_dispc \ Index: boot/arch/arm32/include/cp15.h =================================================================== --- boot/arch/arm32/include/cp15.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) +++ boot/arch/arm32/include/cp15.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -0,0 +1,1 @@ +../../../../kernel/arch/arm32/include/arch/cp15.h Index: boot/arch/arm32/src/asm.S =================================================================== --- boot/arch/arm32/src/asm.S (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/arm32/src/asm.S (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -56,5 +56,4 @@ jump_to_kernel: # - # TODO # Make sure that the I-cache, D-cache and memory are mutually coherent # before passing control to the copied code. @@ -68,10 +67,19 @@ #define CP15_C1_BP 11 #define CP15_C1_DC 2 - # Disable I-cache and D-cache before the kernel is started. + + +#ifndef PROCESSOR_ARCH_armv7_a mrc p15, 0, r4, c1, c0, 0 + + # D-cache before the kernel is started. bic r4, r4, #(1 << CP15_C1_DC) + + # Disable I-cache and Branche predictors. bic r4, r4, #(1 << CP15_C1_IC) bic r4, r4, #(1 << CP15_C1_BP) + mcr p15, 0, r4, c1, c0, 0 +#endif + @@ -81,8 +89,10 @@ #else #cp15 dsb, r4 is ignored (should be zero) + mov r4, #0 mcr p15, 0, r4, c7, c10, 4 #endif # Clean ICache and BPredictors, r4 ignored (SBZ) + mov r4, #0 mcr p15, 0, r4, c7, c5, 0 nop Index: boot/arch/arm32/src/main.c =================================================================== --- boot/arch/arm32/src/main.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/arm32/src/main.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -53,25 +53,9 @@ extern void *bdata_end; - -static inline void invalidate_icache(void) -{ - /* ICIALLU Invalidate entire ICache */ - asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" ); -} - -static inline void invalidate_dcache(void *address, size_t size) -{ - const uintptr_t addr = (uintptr_t)address; - /* DCIMVAC - invalidate by address to the point of coherence */ - for (uintptr_t a = addr; a < addr + size; a += 4) { - asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : ); - } -} - static inline void clean_dcache_poc(void *address, size_t size) { const uintptr_t addr = (uintptr_t)address; - /* DCCMVAC - clean by address to the point of coherence */ for (uintptr_t a = addr; a < addr + size; a += 4) { + /* DCCMVAC - clean by address to the point of coherence */ asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : ); } @@ -82,11 +66,4 @@ void bootstrap(void) { - /* Make sure we run in memory code when caches are enabled, - * make sure we read memory data too. This part is ARMv7 specific as - * ARMv7 no longer invalidates caches on restart. - * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/ - invalidate_icache(); - invalidate_dcache(&bdata_start, &bdata_end - &bdata_start); - /* Enable MMU and caches */ mmu_start(); @@ -105,5 +82,4 @@ components[i].start, components[i].name, components[i].inflated, components[i].size); - invalidate_dcache(components[i].start, components[i].size); } @@ -148,4 +124,5 @@ halt(); } + /* Make sure data are in the memory, ICache will need them */ clean_dcache_poc(dest[i - 1], components[i - 1].inflated); } Index: boot/arch/arm32/src/mm.c =================================================================== --- boot/arch/arm32/src/mm.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/arm32/src/mm.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -37,4 +37,50 @@ #include #include +#include + +#ifdef PROCESSOR_ARCH_armv7_a +static unsigned log2(unsigned val) +{ + unsigned log = 0; + while (val >> log++); + return log - 2; +} + +static void dcache_invalidate_level(unsigned level) +{ + CSSELR_write(level << 1); + const uint32_t ccsidr = CCSIDR_read(); + const unsigned sets = CCSIDR_SETS(ccsidr); + const unsigned ways = CCSIDR_WAYS(ccsidr); + const unsigned line_log = CCSIDR_LINESIZE_LOG(ccsidr); + const unsigned set_shift = line_log; + const unsigned way_shift = 32 - log2(ways); + + for (unsigned k = 0; k < ways; ++k) + for (unsigned j = 0; j < sets; ++j) { + const uint32_t val = (level << 1) | + (j << set_shift) | (k << way_shift); + DCISW_write(val); + } +} + +/** invalidate all dcaches -- armv7 */ +static void cache_invalidate(void) +{ + const uint32_t cinfo = CLIDR_read(); + for (unsigned i = 0; i < 7; ++i) { + switch (CLIDR_CACHE(i, cinfo)) + { + case CLIDR_DCACHE_ONLY: + case CLIDR_SEP_CACHE: + case CLIDR_UNI_CACHE: + dcache_invalidate_level(i); + } + } + asm volatile ( "dsb\n" ); + ICIALLU_write(0); + asm volatile ( "isb\n" ); +} +#endif /** Disable the MMU */ @@ -60,21 +106,16 @@ static inline int section_cacheable(pfn_t section) { + const unsigned long address = section << PTE_SECTION_SHIFT; #ifdef MACHINE_gta02 - unsigned long address = section << PTE_SECTION_SHIFT; - - if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END) - return 0; - else + if (address < GTA02_IOMEM_START || address >= GTA02_IOMEM_END) return 1; #elif defined MACHINE_beagleboardxm - const unsigned long address = section << PTE_SECTION_SHIFT; if (address >= BBXM_RAM_START && address < BBXM_RAM_END) return 1; #elif defined MACHINE_beaglebone - const unsigned long address = section << PTE_SECTION_SHIFT; if (address >= AM335x_RAM_START && address < AM335x_RAM_END) return 1; #endif - return 0; + return address * 0; } @@ -95,11 +136,23 @@ { pte->descriptor_type = PTE_DESCRIPTOR_SECTION; - pte->bufferable = 1; - pte->cacheable = section_cacheable(frame); pte->xn = 0; pte->domain = 0; pte->should_be_zero_1 = 0; pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW; +#ifdef PROCESSOR_ARCH_armv7_a + /* + * Keeps this setting in sync with memory type attributes in: + * init_boot_pt (boot/arch/arm32/src/mm.c) + * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) + * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) + */ + pte->tex = section_cacheable(frame) ? 5 : 0; + pte->cacheable = section_cacheable(frame) ? 0 : 0; + pte->bufferable = section_cacheable(frame) ? 1 : 0; +#else + pte->bufferable = 1; + pte->cacheable = section_cacheable(frame); pte->tex = 0; +#endif pte->access_permission_1 = 0; pte->shareable = 0; @@ -113,14 +166,26 @@ static void init_boot_pt(void) { - const pfn_t split_page = PTL0_ENTRIES; - /* Create 1:1 virtual-physical mapping (in lower 2 GB). */ - pfn_t page; - for (page = 0; page < split_page; page++) + /* + * Create 1:1 virtual-physical mapping. + * Physical memory on BBxM a BBone starts at 2GB + * boundary, icp has a memory mirror at 2GB. + * (ARM Integrator Core Module User guide ch. 6.3, p. 6-7) + * gta02 somehow works (probably due to limited address size), + * s3c2442b manual ch. 5, p.5-1: + * "Address space: 128Mbytes per bank (total 1GB/8 banks)" + */ + for (pfn_t page = 0; page < PTL0_ENTRIES; ++page) init_ptl0_section(&boot_pt[page], page); - - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (boot_pt) - ); + + /* + * Tell MMU page might be cached. Keeps this setting in sync + * with memory type attributes in: + * init_ptl0_section (boot/arch/arm32/src/mm.c) + * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) + * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) + */ + uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK; + val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG; + TTBR0_write(val); } @@ -141,6 +206,12 @@ * we disable caches before jumping to kernel * so this is safe for all archs. + * Enable VMSAv6 the bit (23) is only writable on ARMv6. + * (and QEMU) */ +#ifdef PROCESSOR_ARCH_armv6 + "ldr r1, =0x00801805\n" +#else "ldr r1, =0x00001805\n" +#endif "orr r0, r0, r1\n" @@ -160,4 +231,11 @@ void mmu_start() { disable_paging(); +#ifdef PROCESSOR_ARCH_armv7_a + /* Make sure we run in memory code when caches are enabled, + * make sure we read memory data too. This part is ARMv7 specific as + * ARMv7 no longer invalidates caches on restart. + * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/ + cache_invalidate(); +#endif init_boot_pt(); enable_paging(); Index: boot/arch/mips32/Makefile.inc =================================================================== --- boot/arch/mips32/Makefile.inc (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/mips32/Makefile.inc (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -50,4 +50,17 @@ endif +ifeq ($(MACHINE), $(filter $(MACHINE),bmalta lmalta)) + RD_DRVS_ESSENTIAL += \ + infrastructure/rootmalta \ + block/ata_bd \ + bus/pci/pciintel \ + bus/isa \ + char/i8042 \ + char/ps2mouse \ + char/xtkbd + + RD_DRV_CFG += \ + bus/isa +endif SOURCES = \ Index: boot/arch/ppc32/Makefile.inc =================================================================== --- boot/arch/ppc32/Makefile.inc (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/ppc32/Makefile.inc (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -42,5 +42,5 @@ $(USPACE_PATH)/srv/hw/bus/cuda_adb/cuda_adb -RD_DRVS += \ +RD_DRVS_ESSENTIAL += \ infrastructure/rootmac \ bus/pci/pciintel \ Index: boot/arch/sparc64/src/asm.S =================================================================== --- boot/arch/sparc64/src/asm.S (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ boot/arch/sparc64/src/asm.S (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -30,8 +30,10 @@ #include +#if defined(PROCESSOR_us) || defined(PROCESSOR_us3) #define ICACHE_SIZE 8192 #define ICACHE_LINE_SIZE 32 #define ICACHE_SET_BIT (1 << 13) #define ASI_ICACHE_TAG 0x67 +#endif /* PROCESSOR_us || PROCESSOR_us3 */ .register %g2, #scratch @@ -134,4 +136,5 @@ # Flush I-cache icache_flush: +#if defined(PROCESSOR_us) || defined(PROCESSOR_us3) set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 stxa %g0, [%g1] ASI_ICACHE_TAG @@ -149,4 +152,9 @@ nop +#else + // TODO: sun4v + retl + nop +#endif /* PROCESSOR_us || PROCESSOR_us3 */ .global ofw Index: contrib/conf/ia32-qe.sh =================================================================== --- contrib/conf/ia32-qe.sh (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ contrib/conf/ia32-qe.sh (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -20,3 +20,3 @@ fi -"${QEMU_BINARY}" "$@" -m 32 -hda "$DISK_IMG" -cdrom image.iso -boot d +"${QEMU_BINARY}" "$@" -m 64 -hda "$DISK_IMG" -cdrom image.iso -boot d -soundhw sb16 Index: defaults/sparc64/niagara/Makefile.config =================================================================== --- defaults/sparc64/niagara/Makefile.config (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ defaults/sparc64/niagara/Makefile.config (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -10,2 +10,5 @@ # Framebuffer support CONFIG_FB = n + +# Barebone build with essential binaries only +CONFIG_BAREBONE = y Index: kernel/Makefile =================================================================== --- kernel/Makefile (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/Makefile (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -226,5 +226,4 @@ generic/src/mm/km.c \ generic/src/mm/reserve.c \ - generic/src/mm/buddy.c \ generic/src/mm/frame.c \ generic/src/mm/page.c \ Index: kernel/arch/abs32le/include/arch/mm/frame.h =================================================================== --- kernel/arch/abs32le/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/abs32le/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_LOWPRIO 0 + #include Index: kernel/arch/abs32le/include/arch/mm/page.h =================================================================== --- kernel/arch/abs32le/include/arch/mm/page.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/abs32le/include/arch/mm/page.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -57,8 +57,8 @@ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_FRAMES_ARCH 1 +#define PTL1_FRAMES_ARCH 1 +#define PTL2_FRAMES_ARCH 1 +#define PTL3_FRAMES_ARCH 1 /* Macros calculating indices for each level. */ Index: kernel/arch/amd64/include/arch/mm/frame.h =================================================================== --- kernel/arch/amd64/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/amd64/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_LOWPRIO 0x1000 + #ifndef __ASM__ Index: kernel/arch/amd64/include/arch/mm/page.h =================================================================== --- kernel/arch/amd64/include/arch/mm/page.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/amd64/include/arch/mm/page.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -61,8 +61,8 @@ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH ONE_FRAME -#define PTL2_SIZE_ARCH ONE_FRAME -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_FRAMES_ARCH 1 +#define PTL1_FRAMES_ARCH 1 +#define PTL2_FRAMES_ARCH 1 +#define PTL3_FRAMES_ARCH 1 /* Macros calculating indices into page tables in each level. */ Index: kernel/arch/amd64/src/ddi/ddi.c =================================================================== --- kernel/arch/amd64/src/ddi/ddi.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/amd64/src/ddi/ddi.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -42,4 +42,5 @@ #include #include +#include #include #include @@ -58,27 +59,28 @@ int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) { - size_t bits = ioaddr + size; - if (bits > IO_PORTS) + size_t elements = ioaddr + size; + if (elements > IO_PORTS) return ENOENT; - if (task->arch.iomap.bits < bits) { + if (task->arch.iomap.elements < elements) { /* * The I/O permission bitmap is too small and needs to be grown. */ - uint8_t *newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); - if (!newmap) + void *store = malloc(bitmap_size(elements), FRAME_ATOMIC); + if (!store) return ENOMEM; bitmap_t oldiomap; - bitmap_initialize(&oldiomap, task->arch.iomap.map, + bitmap_initialize(&oldiomap, task->arch.iomap.elements, task->arch.iomap.bits); - bitmap_initialize(&task->arch.iomap, newmap, bits); + + bitmap_initialize(&task->arch.iomap, elements, store); /* * Mark the new range inaccessible. */ - bitmap_set_range(&task->arch.iomap, oldiomap.bits, - bits - oldiomap.bits); + bitmap_set_range(&task->arch.iomap, oldiomap.elements, + elements - oldiomap.elements); /* @@ -88,6 +90,7 @@ if (oldiomap.bits) { bitmap_copy(&task->arch.iomap, &oldiomap, - oldiomap.bits); - free(oldiomap.map); + oldiomap.elements); + + free(oldiomap.bits); } } @@ -96,5 +99,5 @@ * Enable the range and we are done. */ - bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size); + bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, size); /* @@ -118,13 +121,15 @@ /* First, copy the I/O Permission Bitmap. */ irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; - size_t bits = TASK->arch.iomap.bits; - if (bits) { - ASSERT(TASK->arch.iomap.map); + size_t elements = TASK->arch.iomap.elements; + + if (elements > 0) { + ASSERT(TASK->arch.iomap.bits); bitmap_t iomap; - bitmap_initialize(&iomap, CPU->arch.tss->iomap, - TSS_IOMAP_SIZE * 8); - bitmap_copy(&iomap, &TASK->arch.iomap, bits); + bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, + CPU->arch.tss->iomap); + bitmap_copy(&iomap, &TASK->arch.iomap, elements); /* @@ -132,16 +137,19 @@ * I/O access. */ - bitmap_set_range(&iomap, bits, ALIGN_UP(bits, 8) - bits); + bitmap_set_range(&iomap, elements, + ALIGN_UP(elements, 8) - elements); + /* * It is safe to set the trailing eight bits because of the * extra convenience byte in TSS_IOMAP_SIZE. */ - bitmap_set_range(&iomap, ALIGN_UP(bits, 8), 8); + bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8); } + irq_spinlock_unlock(&TASK->lock, false); /* * Second, adjust TSS segment limit. - * Take the extra ending byte will all bits set into account. + * Take the extra ending byte with all bits set into account. */ ptr_16_64_t cpugdtr; @@ -149,5 +157,6 @@ descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base; - gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits)); + size_t size = bitmap_size(elements); + gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size); gdtr_load(&cpugdtr); Index: kernel/arch/amd64/src/proc/task.c =================================================================== --- kernel/arch/amd64/src/proc/task.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/amd64/src/proc/task.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -34,6 +34,7 @@ #include +#include +#include #include -#include /** Perform amd64 specific task initialization. @@ -45,5 +46,5 @@ { task->arch.iomapver = 0; - bitmap_initialize(&task->arch.iomap, NULL, 0); + bitmap_initialize(&task->arch.iomap, 0, NULL); } @@ -55,6 +56,6 @@ void task_destroy_arch(task_t *task) { - if (task->arch.iomap.map) - free(task->arch.iomap.map); + if (task->arch.iomap.bits != NULL) + free(task->arch.iomap.bits); } Index: kernel/arch/arm32/include/arch/asm.h =================================================================== --- kernel/arch/arm32/include/arch/asm.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/include/arch/asm.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -38,4 +38,5 @@ #include +#include #include #include @@ -51,7 +52,7 @@ * chapter 2.3.8 p.2-22 (52 in the PDF) * - * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture - * reference manual for armv4/5 CP15 implementation is mandatory only for - * armv6+. + * @note Although CP15WFI (mcr p15, 0, R0, c7, c0, 4) is defined in ARM + * Architecture reference manual for armv4/5, CP15 implementation is mandatory + * only for armv6+. */ NO_TRACE static inline void cpu_sleep(void) @@ -60,5 +61,5 @@ asm volatile ( "wfe" ); #elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t) - asm volatile ( "mcr p15, 0, R0, c7, c0, 4" ); + WFI_write(0); #endif } Index: kernel/arch/arm32/include/arch/cp15.h =================================================================== --- kernel/arch/arm32/include/arch/cp15.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/include/arch/cp15.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -171,4 +171,11 @@ CCSIDR_LINESIZE_MASK = 0x7, CCSIDR_LINESIZE_SHIFT = 0, +#define CCSIDR_SETS(val) \ + (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1) +#define CCSIDR_WAYS(val) \ + (((val >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1) +/* The register value is log(linesize_in_words) - 2 */ +#define CCSIDR_LINESIZE_LOG(val) \ + (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2) }; CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0); @@ -187,5 +194,6 @@ CLIDR_UNI_CACHE = 0x4, CLIDR_CACHE_MASK = 0x7, -#define CLIDR_CACHE(level, val) ((val >> (level - 1) * 3) & CLIDR_CACHE_MASK) +/** levels counted from 0 */ +#define CLIDR_CACHE(level, val) ((val >> (level * 3)) & CLIDR_CACHE_MASK) }; CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1); @@ -293,4 +301,15 @@ /* Memory protection and control registers */ +enum { + TTBR_ADDR_MASK = 0xffffff80, + TTBR_NOS_FLAG = 1 << 5, + TTBR_RGN_MASK = 0x3 << 3, + TTBR_RGN_NO_CACHE = 0x0 << 3, + TTBR_RGN_WBWA_CACHE = 0x1 << 3, + TTBR_RGN_WT_CACHE = 0x2 << 3, + TTBR_RGN_WB_CACHE = 0x3 << 3, + TTBR_S_FLAG = 1 << 1, + TTBR_C_FLAG = 1 << 0, +}; CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0); CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0); @@ -363,5 +382,5 @@ CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1); -CONTROL_REG_GEN_WRITE(DCIMSW, c7, 0, c6, 2); +CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2); CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); @@ -369,8 +388,8 @@ CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); -CONTROL_REG_GEN_WRITE(ATS1NSOPR, c7, 0, c8, 4); -CONTROL_REG_GEN_WRITE(ATS1NSOPW, c7, 0, c8, 5); -CONTROL_REG_GEN_WRITE(ATS1NSOUR, c7, 0, c8, 6); -CONTROL_REG_GEN_WRITE(ATS1NSOUW, c7, 0, c8, 7); +CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); +CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); +CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); +CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); Index: kernel/arch/arm32/include/arch/mm/frame.h =================================================================== --- kernel/arch/arm32/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_WIDTH 12 /* 4KB frames */ #define FRAME_SIZE (1 << FRAME_WIDTH) + +#define FRAME_LOWPRIO 0 #ifndef __ASM__ Index: kernel/arch/arm32/include/arch/mm/page.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/include/arch/mm/page.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -41,4 +41,5 @@ #include #include +#include #include @@ -72,8 +73,8 @@ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH FOUR_FRAMES -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_FRAMES_ARCH 4 +#define PTL1_FRAMES_ARCH 1 +#define PTL2_FRAMES_ARCH 1 +#define PTL3_FRAMES_ARCH 1 /* Macros calculating indices into page tables for each level. */ @@ -95,11 +96,11 @@ /* Set PTE address accessors for each level. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) \ - (set_ptl0_addr((pte_t *) (ptl0))) + set_ptl0_addr((pte_t *) (ptl0)) #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ - (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10) + set_ptl1_addr((pte_t*) (ptl0), i, a) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ - (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12) + set_ptl3_addr((pte_t*) (ptl3), i, a) /* Get PTE flags accessors for each level. */ @@ -129,4 +130,7 @@ set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) + +#define pt_coherence(page) pt_coherence_m(page, 1) + #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a) #include "page_armv6.h" @@ -137,4 +141,33 @@ #endif +/** Sets the address of level 0 page table. + * + * @param pt Pointer to the page table to set. + * + * Page tables are always in cacheable memory. + * Make sure the memory type is correct, and in sync with: + * init_boot_pt (boot/arch/arm32/src/mm.c) + * init_ptl0_section (boot/arch/arm32/src/mm.c) + * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) + */ +NO_TRACE static inline void set_ptl0_addr(pte_t *pt) +{ + uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK; + val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG; + TTBR0_write(val); +} + +NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address) +{ + pt[i].l0.coarse_table_addr = address >> 10; + pt_coherence(&pt[i].l0); +} + +NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address) +{ + pt[i].l1.frame_base_addr = address >> 12; + pt_coherence(&pt[i].l1); +} + #endif Index: kernel/arch/arm32/include/arch/mm/page_armv4.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv4.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/include/arch/mm/page_armv4.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -120,18 +120,10 @@ #define PTE_DESCRIPTOR_SMALL_PAGE 2 - -/** Sets the address of level 0 page table. - * - * @param pt Pointer to the page table to set. - * - */ -NO_TRACE static inline void set_ptl0_addr(pte_t *pt) -{ - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (pt) - ); -} - +#define pt_coherence_m(pt, count) \ +do { \ + for (unsigned i = 0; i < count; ++i) \ + DCCMVAU_write((uintptr_t)(pt + i)); \ + read_barrier(); \ +} while (0) /** Returns level 0 page table entry flags. @@ -223,5 +215,5 @@ /* default access permission */ - p->access_permission_0 = p->access_permission_1 = + p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW; @@ -229,12 +221,12 @@ if (flags & PAGE_USER) { if (flags & PAGE_READ) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_RO_KERNEL_RW; } if (flags & PAGE_WRITE) { - p->access_permission_0 = p->access_permission_1 = - p->access_permission_2 = p->access_permission_3 = - PTE_AP_USER_RW_KERNEL_RW; + p->access_permission_0 = p->access_permission_1 = + p->access_permission_2 = p->access_permission_3 = + PTE_AP_USER_RW_KERNEL_RW; } } Index: kernel/arch/arm32/include/arch/mm/page_armv6.h =================================================================== --- kernel/arch/arm32/include/arch/mm/page_armv6.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/include/arch/mm/page_armv6.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -40,4 +40,5 @@ #error "Do not include arch specific page.h directly use generic page.h instead" #endif + /* Macros for querying the last-level PTE entries. */ @@ -125,16 +126,37 @@ #define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 -/** Sets the address of level 0 page table. - * - * @param pt Pointer to the page table to set. - * - */ -NO_TRACE static inline void set_ptl0_addr(pte_t *pt) -{ - asm volatile ( - "mcr p15, 0, %[pt], c2, c0, 0\n" - :: [pt] "r" (pt) - ); -} + +/** + * For an ARMv7 implementation that does not include the Large Physical Address Extension, + * and in implementations of architecture versions before ARMv7, if the translation tables + * are held in Write-Back Cacheable memory, the caches must be cleaned to the point of + * unification after writing to the translation tables and before the DSB instruction. This + * ensures that the updated translation table are visible to a hardware translation table walk. + * + * Therefore, an example instruction sequence for writing a translation table entry, + * covering changes to the instruction + * or data mappings in a uniprocessor system is: + * STR rx, [Translation table entry] + * ; write new entry to the translation table + * Clean cache line [Translation table entry] : This operation is not required with the + * ; Multiprocessing Extensions. + * DSB + * ; ensures visibility of the data cleaned from the D Cache + * Invalidate TLB entry by MVA (and ASID if non-global) [page address] + * Invalidate BTC + * DSB + * ; ensure completion of the Invalidate TLB operation + * ISB + * ; ensure table changes visible to instruction fetch + * + * ARM Architecture reference chp. B3.10.1 p. B3-1375 + * @note: see TTRB0/1 for pt memory type + */ +#define pt_coherence_m(pt, count) \ +do { \ + for (unsigned i = 0; i < count; ++i) \ + DCCMVAU_write((uintptr_t)(pt + i)); \ + read_barrier(); \ +} while (0) @@ -206,4 +228,5 @@ p->ns = 0; } + pt_coherence(p); } @@ -232,15 +255,30 @@ p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX; } - - /* tex=0 buf=1 and cache=1 => normal memory - * tex=0 buf=1 and cache=0 => shareable device mmio - */ - p->cacheable = (flags & PAGE_CACHEABLE); - p->bufferable = 1; - p->tex = 0; + + if (flags & PAGE_CACHEABLE) { + /* + * Write-through, no write-allocate memory, see ch. B3.8.2 + * (p. B3-1358) of ARM Architecture reference manual. + * Make sure the memory type is correct, and in sync with: + * init_boot_pt (boot/arch/arm32/src/mm.c) + * init_ptl0_section (boot/arch/arm32/src/mm.c) + * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) + */ + p->tex = 5; + p->cacheable = 0; + p->bufferable = 1; + } else { + /* + * Shareable device memory, see ch. B3.8.2 (p. B3-1358) of + * ARM Architecture reference manual. + */ + p->tex = 0; + p->cacheable = 0; + p->bufferable = 1; + } /* Shareable is ignored for devices (non-cacheable), - * turn it on for normal memory. */ - p->shareable = 1; + * turn it off for normal memory. */ + p->shareable = 0; p->non_global = !(flags & PAGE_GLOBAL); @@ -256,4 +294,5 @@ p->access_permission_1 = PTE_AP1_RO; } + pt_coherence(p); } @@ -264,6 +303,6 @@ p->should_be_zero_0 = 0; p->should_be_zero_1 = 0; - write_barrier(); p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; + pt_coherence(p); } @@ -273,4 +312,5 @@ p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; + pt_coherence(p); } Index: kernel/arch/arm32/src/cpu/cpu.c =================================================================== --- kernel/arch/arm32/src/cpu/cpu.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/src/cpu/cpu.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -157,5 +157,5 @@ #endif #ifdef PROCESSOR_ARCH_armv7_a - /* ICache coherency is elaborate on in barrier.h. + /* ICache coherency is elaborated on in barrier.h. * VIPT and PIPT caches need maintenance only on code modify, * so it should be safe for general use. @@ -166,4 +166,7 @@ control_reg |= SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG; + } else { + control_reg &= + ~(SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG); } #endif @@ -204,7 +207,6 @@ #ifdef PROCESSOR_ARCH_armv7_a CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT); - const unsigned ls_log = 2 + - ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK); - return ls_log + 2; //return log2(bytes) + const uint32_t ccsidr = CCSIDR_read(); + return CCSIDR_LINESIZE_LOG(ccsidr); #endif return 0; @@ -217,7 +219,6 @@ #ifdef PROCESSOR_ARCH_armv7_a CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT); - const unsigned ways = 1 + - ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK); - return ways; + const uint32_t ccsidr = CCSIDR_read(); + return CCSIDR_WAYS(ccsidr); #endif return 0; @@ -229,7 +230,6 @@ #ifdef PROCESSOR_ARCH_armv7_a CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT); - const unsigned sets = 1 + - ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK); - return sets; + const uint32_t ccsidr = CCSIDR_read(); + return CCSIDR_SETS(ccsidr); #endif return 0; @@ -241,5 +241,5 @@ #ifdef PROCESSOR_ARCH_armv7_a const uint32_t val = CLIDR_read(); - for (unsigned i = 1; i <= 7; ++i) { + for (unsigned i = 0; i < 8; ++i) { const unsigned ctype = CLIDR_CACHE(i, val); switch (ctype) { @@ -280,5 +280,5 @@ const unsigned ways = dcache_ways(i); const unsigned sets = dcache_sets(i); - const unsigned way_shift = 31 - log2(ways); + const unsigned way_shift = 32 - log2(ways); const unsigned set_shift = dcache_linesize_log(i); dcache_clean_manual(i, false, ways, sets, way_shift, set_shift); @@ -293,5 +293,5 @@ const unsigned ways = dcache_ways(i); const unsigned sets = dcache_sets(i); - const unsigned way_shift = 31 - log2(ways); + const unsigned way_shift = 32 - log2(ways); const unsigned set_shift = dcache_linesize_log(i); dcache_clean_manual(i, true, ways, sets, way_shift, set_shift); Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c =================================================================== --- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -60,5 +60,5 @@ static struct beagleboard { - amdm37x_irc_regs_t *irc_addr; + omap_irc_regs_t *irc_addr; omap_uart_t uart; amdm37x_gpt_t timer; @@ -85,9 +85,10 @@ static void bb_timer_irq_handler(irq_t *irq) { + amdm37x_gpt_irq_ack(&beagleboard.timer); + /* * We are holding a lock which prevents preemption. * Release the lock, call clock() and reacquire the lock again. */ - amdm37x_gpt_irq_ack(&beagleboard.timer); spinlock_unlock(&irq->lock); clock(); @@ -102,5 +103,5 @@ PAGE_NOT_CACHEABLE); ASSERT(beagleboard.irc_addr); - amdm37x_irc_init(beagleboard.irc_addr); + omap_irc_init(beagleboard.irc_addr); /* Initialize timer. Use timer1, because it is in WKUP power domain @@ -122,5 +123,5 @@ /* Enable timer interrupt */ - amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ); + omap_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ); /* Start timer here */ @@ -146,6 +147,5 @@ static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate) { - const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr); - amdm37x_irc_irq_ack(beagleboard.irc_addr); + const unsigned inum = omap_irc_inum_get(beagleboard.irc_addr); irq_t *irq = irq_dispatch_and_lock(inum); @@ -159,4 +159,7 @@ CPU->id, inum); } + /** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end + * of ISR. DO this to avoid strange behavior. */ + omap_irc_irq_ack(beagleboard.irc_addr); } @@ -185,5 +188,5 @@ indev_t *srln = srln_wire(srln_instance, sink); omap_uart_input_wire(&beagleboard.uart, srln); - amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ); + omap_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ); } #endif Index: kernel/arch/arm32/src/mach/beaglebone/beaglebone.c =================================================================== --- kernel/arch/arm32/src/mach/beaglebone/beaglebone.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/src/mach/beaglebone/beaglebone.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -63,5 +63,5 @@ static struct beaglebone { - am335x_irc_regs_t *irc_addr; + omap_irc_regs_t *irc_addr; am335x_cm_per_regs_t *cm_per_addr; am335x_cm_dpll_regs_t *cm_dpll_addr; @@ -104,5 +104,5 @@ /* Initialize the interrupt controller */ - am335x_irc_init(bbone.irc_addr); + omap_irc_init(bbone.irc_addr); } @@ -153,5 +153,5 @@ } /* Enable the interrupt */ - am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ); + omap_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ); /* Start the timer */ am335x_timer_start(&bbone.timer); @@ -176,5 +176,5 @@ static void bbone_irq_exception(unsigned int exc_no, istate_t *istate) { - const unsigned inum = am335x_irc_inum_get(bbone.irc_addr); + const unsigned inum = omap_irc_inum_get(bbone.irc_addr); irq_t *irq = irq_dispatch_and_lock(inum); @@ -187,5 +187,5 @@ } - am335x_irc_irq_ack(bbone.irc_addr); + omap_irc_irq_ack(bbone.irc_addr); } @@ -214,5 +214,5 @@ indev_t *srln = srln_wire(srln_instance, sink); omap_uart_input_wire(&bbone.uart, srln); - am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ); + omap_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ); } #endif Index: kernel/arch/arm32/src/mm/frame.c =================================================================== --- kernel/arch/arm32/src/mm/frame.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/src/mm/frame.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -88,7 +88,6 @@ void boot_page_table_free(void) { - unsigned int i; - for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++) - frame_free(i * FRAME_SIZE + BOOT_PAGE_TABLE_ADDRESS); + frame_free(BOOT_PAGE_TABLE_ADDRESS, + BOOT_PAGE_TABLE_SIZE_IN_FRAMES); } Index: kernel/arch/arm32/src/mm/page.c =================================================================== --- kernel/arch/arm32/src/mm/page.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/src/mm/page.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -69,5 +69,5 @@ #ifdef HIGH_EXCEPTION_VECTORS /* Create mapping for exception table at high offset */ - uintptr_t ev_frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_NONE); + uintptr_t ev_frame = frame_alloc(1, FRAME_NONE, 0); page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, ev_frame, flags); #else Index: kernel/arch/arm32/src/mm/tlb.c =================================================================== --- kernel/arch/arm32/src/mm/tlb.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/src/mm/tlb.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -37,6 +37,8 @@ #include #include +#include #include #include +#include /** Invalidate all entries in TLB. @@ -46,9 +48,17 @@ void tlb_invalidate_all(void) { - asm volatile ( - "eor r1, r1\n" - "mcr p15, 0, r1, c8, c7, 0\n" - ::: "r1" - ); + TLBIALL_write(0); + /* + * "A TLB maintenance operation is only guaranteed to be complete after + * the execution of a DSB instruction." + * "An ISB instruction, or a return from an exception, causes the + * effect of all completed TLB maintenance operations that appear in + * program order before the ISB or return from exception to be visible + * to all subsequent instructions, including the instruction fetches + * for those instructions." + * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375 + */ + read_barrier(); + inst_barrier(); } @@ -60,4 +70,5 @@ { tlb_invalidate_all(); + // TODO: why not TLBIASID_write(asid) ? } @@ -65,11 +76,21 @@ * * @param page Virtual adress of the page - */ + */ static inline void invalidate_page(uintptr_t page) { - asm volatile ( - "mcr p15, 0, %[page], c8, c7, 1\n" - :: [page] "r" (page) - ); + //TODO: What about TLBIMVAA? + TLBIMVA_write(page); + /* + * "A TLB maintenance operation is only guaranteed to be complete after + * the execution of a DSB instruction." + * "An ISB instruction, or a return from an exception, causes the + * effect of all completed TLB maintenance operations that appear in + * program order before the ISB or return from exception to be visible + * to all subsequent instructions, including the instruction fetches + * for those instructions." + * ARM Architecture reference Manual ch. B3.10.1 p. B3-1374 B3-1375 + */ + read_barrier(); + inst_barrier(); } @@ -83,7 +104,5 @@ void tlb_invalidate_pages(asid_t asid __attribute__((unused)), uintptr_t page, size_t cnt) { - unsigned int i; - - for (i = 0; i < cnt; i++) + for (unsigned i = 0; i < cnt; i++) invalidate_page(page + i * PAGE_SIZE); } Index: kernel/arch/arm32/src/ras.c =================================================================== --- kernel/arch/arm32/src/ras.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/arm32/src/ras.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -51,13 +51,12 @@ void ras_init(void) { - uintptr_t frame; - - frame = (uintptr_t) frame_alloc(ONE_FRAME, - FRAME_ATOMIC | FRAME_HIGHMEM); + uintptr_t frame = + frame_alloc(1, FRAME_ATOMIC | FRAME_HIGHMEM, 0); if (!frame) - frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_LOWMEM); + frame = frame_alloc(1, FRAME_LOWMEM, 0); + ras_page = (uintptr_t *) km_map(frame, PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE); - + memsetb(ras_page, PAGE_SIZE, 0); ras_page[RAS_START] = 0; Index: kernel/arch/ia32/include/arch/mm/frame.h =================================================================== --- kernel/arch/ia32/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ia32/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_LOWPRIO 0x1000 + #ifndef __ASM__ Index: kernel/arch/ia32/include/arch/mm/page.h =================================================================== --- kernel/arch/ia32/include/arch/mm/page.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ia32/include/arch/mm/page.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -66,8 +66,8 @@ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_FRAMES_ARCH 1 +#define PTL1_FRAMES_ARCH 1 +#define PTL2_FRAMES_ARCH 1 +#define PTL3_FRAMES_ARCH 1 /* Macros calculating indices for each level. */ Index: kernel/arch/ia32/src/ddi/ddi.c =================================================================== --- kernel/arch/ia32/src/ddi/ddi.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ia32/src/ddi/ddi.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -59,27 +59,28 @@ int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) { - size_t bits = ioaddr + size; - if (bits > IO_PORTS) + size_t elements = ioaddr + size; + if (elements > IO_PORTS) return ENOENT; - if (task->arch.iomap.bits < bits) { + if (task->arch.iomap.elements < elements) { /* * The I/O permission bitmap is too small and needs to be grown. */ - uint8_t *newmap = (uint8_t *) malloc(BITS2BYTES(bits), FRAME_ATOMIC); - if (!newmap) + void *store = malloc(bitmap_size(elements), FRAME_ATOMIC); + if (!store) return ENOMEM; bitmap_t oldiomap; - bitmap_initialize(&oldiomap, task->arch.iomap.map, + bitmap_initialize(&oldiomap, task->arch.iomap.elements, task->arch.iomap.bits); - bitmap_initialize(&task->arch.iomap, newmap, bits); + + bitmap_initialize(&task->arch.iomap, elements, store); /* * Mark the new range inaccessible. */ - bitmap_set_range(&task->arch.iomap, oldiomap.bits, - bits - oldiomap.bits); + bitmap_set_range(&task->arch.iomap, oldiomap.elements, + elements - oldiomap.elements); /* @@ -89,6 +90,7 @@ if (oldiomap.bits) { bitmap_copy(&task->arch.iomap, &oldiomap, - oldiomap.bits); - free(oldiomap.map); + oldiomap.elements); + + free(oldiomap.bits); } } @@ -97,5 +99,5 @@ * Enable the range and we are done. */ - bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, (size_t) size); + bitmap_clear_range(&task->arch.iomap, (size_t) ioaddr, size); /* @@ -119,13 +121,15 @@ /* First, copy the I/O Permission Bitmap. */ irq_spinlock_lock(&TASK->lock, false); + size_t ver = TASK->arch.iomapver; - size_t bits = TASK->arch.iomap.bits; - if (bits) { - ASSERT(TASK->arch.iomap.map); + size_t elements = TASK->arch.iomap.elements; + + if (elements > 0) { + ASSERT(TASK->arch.iomap.bits); bitmap_t iomap; - bitmap_initialize(&iomap, CPU->arch.tss->iomap, - TSS_IOMAP_SIZE * 8); - bitmap_copy(&iomap, &TASK->arch.iomap, bits); + bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, + CPU->arch.tss->iomap); + bitmap_copy(&iomap, &TASK->arch.iomap, elements); /* @@ -133,11 +137,14 @@ * I/O access. */ - bitmap_set_range(&iomap, bits, ALIGN_UP(bits, 8) - bits); + bitmap_set_range(&iomap, elements, + ALIGN_UP(elements, 8) - elements); + /* * It is safe to set the trailing eight bits because of the * extra convenience byte in TSS_IOMAP_SIZE. */ - bitmap_set_range(&iomap, ALIGN_UP(bits, 8), 8); + bitmap_set_range(&iomap, ALIGN_UP(elements, 8), 8); } + irq_spinlock_unlock(&TASK->lock, false); @@ -150,5 +157,6 @@ descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base; - gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits)); + size_t size = bitmap_size(elements); + gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size); gdtr_load(&cpugdtr); Index: kernel/arch/ia32/src/proc/task.c =================================================================== --- kernel/arch/ia32/src/proc/task.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ia32/src/proc/task.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -40,20 +40,22 @@ /** Perform ia32 specific task initialization. * - * @param t Task to be initialized. + * @param task Task to be initialized. + * */ -void task_create_arch(task_t *t) +void task_create_arch(task_t *task) { - t->arch.iomapver = 0; - bitmap_initialize(&t->arch.iomap, NULL, 0); + task->arch.iomapver = 0; + bitmap_initialize(&task->arch.iomap, 0, NULL); } /** Perform ia32 specific task destruction. * - * @param t Task to be initialized. + * @param task Task to be initialized. + * */ -void task_destroy_arch(task_t *t) +void task_destroy_arch(task_t *task) { - if (t->arch.iomap.map) - free(t->arch.iomap.map); + if (task->arch.iomap.bits != NULL) + free(task->arch.iomap.bits); } Index: kernel/arch/ia64/include/arch/mm/frame.h =================================================================== --- kernel/arch/ia64/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ia64/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_LOWPRIO 0 + #ifndef __ASM__ Index: kernel/arch/ia64/src/ddi/ddi.c =================================================================== --- kernel/arch/ia64/src/ddi/ddi.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ia64/src/ddi/ddi.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -1,5 +1,5 @@ /* * Copyright (c) 2006 Jakub Jermar - * Copyright (c) 2008 Jakub vana + * Copyright (c) 2008 Jakub Vana * All rights reserved. * @@ -56,11 +56,13 @@ { if (!task->arch.iomap) { - uint8_t *map; - task->arch.iomap = malloc(sizeof(bitmap_t), 0); - map = malloc(BITS2BYTES(IO_MEMMAP_PAGES), 0); - if(!map) + if (task->arch.iomap == NULL) return ENOMEM; - bitmap_initialize(task->arch.iomap, map, IO_MEMMAP_PAGES); + + void *store = malloc(bitmap_size(IO_MEMMAP_PAGES), 0); + if (store == NULL) + return ENOMEM; + + bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, store); bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES); } @@ -69,5 +71,5 @@ size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE); bitmap_set_range(task->arch.iomap, iopage, size / 4); - + return 0; } Index: kernel/arch/ia64/src/mm/vhpt.c =================================================================== --- kernel/arch/ia64/src/mm/vhpt.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ia64/src/mm/vhpt.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -42,8 +42,10 @@ uintptr_t vhpt_set_up(void) { - vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH, - FRAME_KA | FRAME_ATOMIC); - if (!vhpt_base) + uintptr_t vhpt_frame = + frame_alloc(SIZE2FRAMES(VHPT_SIZE), FRAME_ATOMIC, 0); + if (!vhpt_frame) panic("Kernel configured with VHPT but no memory for table."); + + vhpt_base = (vhpt_entry_t *) PA2KA(vhpt_frame); vhpt_invalidate_all(); return (uintptr_t) vhpt_base; @@ -82,5 +84,5 @@ void vhpt_invalidate_all() { - memsetb(vhpt_base, 1 << VHPT_WIDTH, 0); + memsetb(vhpt_base, VHPT_SIZE, 0); } Index: kernel/arch/mips32/include/arch/asm.h =================================================================== --- kernel/arch/mips32/include/arch/asm.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/mips32/include/arch/asm.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -42,12 +42,5 @@ NO_TRACE static inline void cpu_sleep(void) { - /* - * Unfortunatelly most of the simulators do not support - * - * asm volatile ( - * "wait" - * ); - * - */ + asm volatile ("wait"); } Index: kernel/arch/mips32/include/arch/mm/frame.h =================================================================== --- kernel/arch/mips32/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/mips32/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_LOWPRIO 0 + #ifndef __ASM__ Index: kernel/arch/mips32/include/arch/mm/page.h =================================================================== --- kernel/arch/mips32/include/arch/mm/page.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/mips32/include/arch/mm/page.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -27,5 +27,5 @@ */ -/** @addtogroup mips32mm +/** @addtogroup mips32mm * @{ */ @@ -70,27 +70,27 @@ * - PTL3 has 4096 entries (12 bits) */ - + /* Macros describing number of entries in each level. */ -#define PTL0_ENTRIES_ARCH 64 -#define PTL1_ENTRIES_ARCH 0 -#define PTL2_ENTRIES_ARCH 0 -#define PTL3_ENTRIES_ARCH 4096 +#define PTL0_ENTRIES_ARCH 64 +#define PTL1_ENTRIES_ARCH 0 +#define PTL2_ENTRIES_ARCH 0 +#define PTL3_ENTRIES_ARCH 4096 /* Macros describing size of page tables in each level. */ -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_FRAMES_ARCH 1 +#define PTL1_FRAMES_ARCH 1 +#define PTL2_FRAMES_ARCH 1 +#define PTL3_FRAMES_ARCH 1 /* Macros calculating entry indices for each level. */ -#define PTL0_INDEX_ARCH(vaddr) ((vaddr) >> 26) -#define PTL1_INDEX_ARCH(vaddr) 0 -#define PTL2_INDEX_ARCH(vaddr) 0 -#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 14) & 0xfff) +#define PTL0_INDEX_ARCH(vaddr) ((vaddr) >> 26) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 14) & 0xfff) /* Set accessor for PTL0 address. */ #define SET_PTL0_ADDRESS_ARCH(ptl0) -/* Get PTE address accessors for each level. */ +/* Get PTE address accessors for each level. */ #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ (((pte_t *) (ptl0))[(i)].pfn << 12) @@ -196,5 +196,4 @@ p->p = 1; } - extern void page_arch_init(void); Index: kernel/arch/mips32/src/mach/malta/malta.c =================================================================== --- kernel/arch/mips32/src/mach/malta/malta.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/mips32/src/mach/malta/malta.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -103,4 +103,5 @@ void malta_input_init(void) { + (void) stdin_wire(); } Index: kernel/arch/mips32/src/mm/tlb.c =================================================================== --- kernel/arch/mips32/src/mm/tlb.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/mips32/src/mm/tlb.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -48,14 +48,16 @@ #include -#define PFN_SHIFT 12 -#define VPN_SHIFT 12 -#define ADDR2VPN(a) ((a) >> VPN_SHIFT) -#define ADDR2VPN2(a) (ADDR2VPN((a)) >> 1) -#define VPN2ADDR(vpn) ((vpn) << VPN_SHIFT) -#define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1) -#define PFN2ADDR(pfn) ((pfn) << PFN_SHIFT) - -#define BANK_SELECT_BIT(a) (((a) >> PAGE_WIDTH) & 1) - +#define PFN_SHIFT 12 +#define VPN_SHIFT 12 + +#define ADDR2HI_VPN(a) ((a) >> VPN_SHIFT) +#define ADDR2HI_VPN2(a) (ADDR2HI_VPN((a)) >> 1) + +#define HI_VPN2ADDR(vpn) ((vpn) << VPN_SHIFT) +#define HI_VPN22ADDR(vpn2) (HI_VPN2ADDR(vpn2) << 1) + +#define LO_PFN2ADDR(pfn) ((pfn) << PFN_SHIFT) + +#define BANK_SELECT_BIT(a) (((a) >> PAGE_WIDTH) & 1) /** Initialize TLB. @@ -266,5 +268,5 @@ { hi->value = 0; - hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE)); + hi->vpn2 = ADDR2HI_VPN2(ALIGN_DOWN(addr, PAGE_SIZE)); hi->asid = asid; } @@ -295,8 +297,8 @@ printf("%-4u %-6u %0#10x %-#6x %1u%1u%1u%1u %0#10x\n", - i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask, - lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn)); + i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask, + lo0.g, lo0.v, lo0.d, lo0.c, LO_PFN2ADDR(lo0.pfn)); printf(" %1u%1u%1u%1u %0#10x\n", - lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn)); + lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn)); } Index: kernel/arch/mips64/include/arch/mm/frame.h =================================================================== --- kernel/arch/mips64/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/mips64/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_LOWPRIO 0 + #ifndef __ASM__ Index: kernel/arch/ppc32/include/arch/mm/frame.h =================================================================== --- kernel/arch/ppc32/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ppc32/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,6 @@ #define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_LOWPRIO 0 + #ifndef __ASM__ Index: kernel/arch/ppc32/include/arch/mm/page.h =================================================================== --- kernel/arch/ppc32/include/arch/mm/page.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/ppc32/include/arch/mm/page.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -70,8 +70,8 @@ /* Page table sizes for each level. */ -#define PTL0_SIZE_ARCH ONE_FRAME -#define PTL1_SIZE_ARCH 0 -#define PTL2_SIZE_ARCH 0 -#define PTL3_SIZE_ARCH ONE_FRAME +#define PTL0_FRAMES_ARCH 1 +#define PTL1_FRAMES_ARCH 1 +#define PTL2_FRAMES_ARCH 1 +#define PTL3_FRAMES_ARCH 1 /* Macros calculating indices into page tables on each level. */ Index: kernel/arch/sparc64/include/arch/mm/frame.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/include/arch/mm/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -46,4 +46,16 @@ #endif +#ifndef __ASM__ + +#include + +extern uintptr_t end_of_identity; + +extern void frame_low_arch_init(void); +extern void frame_high_arch_init(void); +#define physmem_print() + +#endif + #endif Index: kernel/arch/sparc64/include/arch/mm/sun4u/frame.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/include/arch/mm/sun4u/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64mm +/** @addtogroup sparc64mm * @{ */ @@ -41,6 +41,6 @@ * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. */ -#define MMU_FRAME_WIDTH 13 /* 8K */ -#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) +#define MMU_FRAME_WIDTH 13 /* 8K */ +#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) /* @@ -49,6 +49,8 @@ * each 16K page with a pair of adjacent 8K pages. */ -#define FRAME_WIDTH 14 /* 16K */ -#define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_WIDTH 14 /* 16K */ +#define FRAME_SIZE (1 << FRAME_WIDTH) + +#define FRAME_LOWPRIO 0 #ifndef __ASM__ @@ -72,10 +74,4 @@ typedef union frame_address frame_address_t; -extern uintptr_t end_of_identity; - -extern void frame_low_arch_init(void); -extern void frame_high_arch_init(void); -#define physmem_print() - #endif Index: kernel/arch/sparc64/include/arch/mm/sun4v/frame.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/frame.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/include/arch/mm/sun4v/frame.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -27,5 +27,5 @@ */ -/** @addtogroup sparc64mm +/** @addtogroup sparc64mm * @{ */ @@ -36,19 +36,11 @@ #define KERN_sparc64_sun4v_FRAME_H_ -#define MMU_FRAME_WIDTH 13 /* 8K */ -#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) +#define MMU_FRAME_WIDTH 13 /* 8K */ +#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) -#define FRAME_WIDTH 13 -#define FRAME_SIZE (1 << FRAME_WIDTH) +#define FRAME_WIDTH 13 +#define FRAME_SIZE (1 << FRAME_WIDTH) -#ifndef __ASM__ - -#include - -extern void frame_low_arch_init(void); -extern void frame_high_arch_init(void); -#define physmem_print() - -#endif +#define FRAME_LOWPRIO 0 #endif Index: kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -102,4 +102,11 @@ nop + /* exclude pages beyond the end of memory from the identity mapping */ + sethi %hi(end_of_identity), %g4 + ldx [%g4 + %lo(end_of_identity)], %g4 + cmp %g1, %g4 + bgeu %xcc, 0f + nop + /* * Installing the identity does not fit into 32 instructions, call Index: kernel/arch/sparc64/src/mm/sun4u/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4u/as.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/src/mm/sun4u/as.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -63,40 +63,30 @@ { #ifdef CONFIG_TSB - /* - * The order must be calculated with respect to the emulated - * 16K page size. - * - */ - uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * - sizeof(tsb_entry_t)) >> FRAME_WIDTH); - - uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); - - if (!tsb) + uintptr_t tsb_phys = + frame_alloc(SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * + sizeof(tsb_entry_t)), flags, 0); + if (!tsb_phys) return -1; - as->arch.itsb = (tsb_entry_t *) tsb; - as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * + tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_phys); + + as->arch.itsb = tsb; + as->arch.dtsb = tsb + ITSB_ENTRY_COUNT; + + memsetb(as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * + sizeof(tsb_entry_t), 0); +#endif + + return 0; +} + +int as_destructor_arch(as_t *as) +{ +#ifdef CONFIG_TSB + size_t frames = SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t)); - - memsetb(as->arch.itsb, - (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); -#endif - - return 0; -} - -int as_destructor_arch(as_t *as) -{ -#ifdef CONFIG_TSB - /* - * The count must be calculated with respect to the emualted 16K page - * size. - */ - size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * - sizeof(tsb_entry_t)) >> FRAME_WIDTH; - frame_free(KA2PA((uintptr_t) as->arch.itsb)); - - return cnt; + frame_free(KA2PA((uintptr_t) as->arch.itsb), frames); + + return frames; #else return 0; Index: kernel/arch/sparc64/src/mm/sun4v/as.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/as.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/src/mm/sun4v/as.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -66,9 +66,7 @@ { #ifdef CONFIG_TSB - uint8_t order = fnzb32( - (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH); - - uintptr_t tsb = (uintptr_t) frame_alloc(order, flags); - + uintptr_t tsb = + frame_alloc(SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)), + flags, 0); if (!tsb) return -1; @@ -92,8 +90,8 @@ { #ifdef CONFIG_TSB - size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH; - frame_free((uintptr_t) as->arch.tsb_description.tsb_base); + size_t frames = SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)); + frame_free(as->arch.tsb_description.tsb_base, frames); - return cnt; + return frames; #else return 0; Index: kernel/arch/sparc64/src/mm/sun4v/frame.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/frame.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/src/mm/sun4v/frame.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -101,4 +101,7 @@ */ frame_mark_unavailable(ADDR2PFN(KA2PA(PFN2ADDR(0))), 1); + + /* PA2KA will work only on low-memory. */ + end_of_identity = PA2KA(config.physmem_end - FRAME_SIZE) + PAGE_SIZE; } Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c =================================================================== --- kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/src/mm/sun4v/tlb.c (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -251,4 +251,5 @@ uintptr_t va = DMISS_ADDRESS(page_and_ctx); uint16_t ctx = DMISS_CONTEXT(page_and_ctx); + as_t *as = AS; if (ctx == ASID_KERNEL) { @@ -256,9 +257,13 @@ /* NULL access in kernel */ panic("NULL pointer dereference."); + } else if (va >= end_of_identity) { + /* Kernel non-identity */ + as = AS_KERNEL; + } else { + panic("Unexpected kernel page fault."); } - panic("Unexpected kernel page fault."); - } - - t = page_mapping_find(AS, va, true); + } + + t = page_mapping_find(as, va, true); if (t) { /* @@ -295,6 +300,10 @@ uintptr_t va = DMISS_ADDRESS(page_and_ctx); uint16_t ctx = DMISS_CONTEXT(page_and_ctx); - - t = page_mapping_find(AS, va, true); + as_t *as = AS; + + if (ctx == ASID_KERNEL) + as = AS_KERNEL; + + t = page_mapping_find(as, va, true); if (t && PTE_WRITABLE(t)) { /* Index: kernel/arch/sparc64/src/sun4v/start.S =================================================================== --- kernel/arch/sparc64/src/sun4v/start.S (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/arch/sparc64/src/sun4v/start.S (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -345,4 +345,13 @@ .quad 0 +/* + * This variable is used by the fast_data_access_MMU_miss trap handler. + * In runtime, it is modified to contain the address of the end of physical + * memory. + */ +.global end_of_identity +end_of_identity: + .quad -1 + .global kernel_8k_tlb_data_template kernel_8k_tlb_data_template: Index: kernel/doc/mm =================================================================== --- kernel/doc/mm (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/doc/mm (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -71,5 +71,5 @@ 'malloc' function accepts flags as a second argument. The flags are directly -passed to the underlying frame_alloc function. +passed to the underlying frame_alloc function. 1) If the flags parameter contains FRAME_ATOMIC, the allocator will not sleep. Index: kernel/genarch/include/genarch/drivers/am335x/irc.h =================================================================== --- kernel/genarch/include/genarch/drivers/am335x/irc.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/genarch/include/genarch/drivers/am335x/irc.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -38,214 +38,14 @@ #define KERN_AM335x_IRQC_H_ -#define AM335x_IRC_BASE_ADDRESS 0x48200000 -#define AM335x_IRC_SIZE 4096 +#define AM335x_IRC_BASE_ADDRESS 0x48200000 +#define AM335x_IRC_SIZE 4096 -#define AM335x_IRC_IRQ_COUNT 128 +#define AM335x_IRC_IRQ_COUNT 128 +#define AM335x_IRC_IRQ_GROUPS_COUNT 4 -#include +#define OMAP_IRC_IRQ_COUNT AM335x_IRC_IRQ_COUNT +#define OMAP_IRC_IRQ_GROUPS_COUNT AM335x_IRC_IRQ_GROUPS_COUNT -typedef struct { - const ioport32_t revision; -#define AM335x_IRC_REV_MASK 0xFF - - const uint8_t padd0[12]; - - /* This register controls the various parameters - * of the OCP interface. - */ - ioport32_t sysconfig; -#define AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) -#define AM335x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) - - /* This register provides status information about the module */ - const ioport32_t sysstatus; -#define AM335x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0) - - const uint8_t padd1[40]; - - /* This register supplies the currently active IRQ interrupt number */ - ioport32_t sir_irq; -#define AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK 0x7F -#define AM335x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 - - /* This register supplies the currently active FIQ interrupt number */ - const ioport32_t sir_fiq; -#define AM335x_IRC_FIQ_IRQ_ACTIVEFIQ_MASK 0x7F -#define AM335x_IRC_FIQ_IRQ_SPURIOUSFIQFLAG_MASK 0xFFFFFFF8 - - /* This register contains the new interrupt agreement bits */ - ioport32_t control; -#define AM335x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0) -#define AM335x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) - - /* This register controls protection of the other registers. - * This register can only be accessed in priviledged mode, regardless - * of the current value of the protection bit. - */ - ioport32_t protection; -#define AM335x_IRC_PROTECTION_FLAG (1 << 0) - - /* This register controls the clock auto-idle for the functional - * clock and the input synchronizers. - */ - ioport32_t idle; -#define AM335x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0) -#define AM335x_IRC_IDLE_TURBO_FLAG (1 << 1) - - const uint8_t padd2[12]; - - /* This register supplies the currently active IRQ priority level */ - const ioport32_t irq_priority; -#define AM335x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK 0x7F -#define AM335x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 - - /* This register supplies the currently active FIQ priority level */ - const ioport32_t fiq_priority; -#define AM335x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK 0x7F -#define AM335x_IRC_FIQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 - - /* This register sets the priority threshold */ - ioport32_t threshold; -#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK 0xFF -#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED 0x00 -#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED 0xFF - - const uint8_t padd[20]; - - struct { - /* Raw interrupt input status before masking */ - const ioport32_t itr; - - /* Interrupt mask */ - ioport32_t mir; - - /* This register is used to clear the interrupt mask bits, - * Write 1 clears the mask bit to 0. - */ - ioport32_t mir_clear; - - /* This register is used to set the interrupt mask bits, - * Write 1 sets the mask bit to 1. - */ - ioport32_t mir_set; - - /* This register is used to set the software interrupt bits, - * it is also used to read the current active software - * interrupts. - * Write 1 sets the software interrups bits to 1. - */ - ioport32_t isr_set; - - /* This register is used to clear the software interrups bits. - * Write 1 clears the software interrupt bits to 0. - */ - ioport32_t isr_clear; - - /* This register contains the IRQ status after masking. */ - const ioport32_t pending_irq; - - /* This register contains the FIQ status after masking. */ - const ioport32_t pending_fiq; - } interrupts[4]; - - /* These registers contain the priority for the interrups and - * the FIQ/IRQ steering. - */ - ioport32_t ilr[AM335x_IRC_IRQ_COUNT]; -/* 0 = Interrupt routed to IRQ, 1 = interrupt routed to FIQ */ -#define AM335x_IRC_ILR_FIQNIRQ_FLAG (1 << 0) -#define AM335x_IRC_ILR_PRIORITY_MASK 0x3F -#define AM335x_IRC_ILR_PRIORITY_SHIFT 2 - -} am335x_irc_regs_t; - -static inline void am335x_irc_init(am335x_irc_regs_t *regs) -{ - int i; - - /* Initialization sequence */ - - /* 1 - Program the SYSCONFIG register: if necessary, enable the - * autogating by setting the AUTOIDLE bit. - */ - regs->sysconfig &= ~AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG; - - /* 2 - Program the IDLE register: if necessary, disable functional - * clock autogating or enable synchronizer autogating by setting - * the FUNCIDLE bit or the TURBO bit accordingly. - */ - regs->idle &= ~AM335x_IRC_IDLE_FUNCIDLE_FLAG; - regs->idle &= ~AM335x_IRC_IDLE_TURBO_FLAG; - - /* 3 - Program ILRm register for each interrupt line: Assign a - * priority level and set the FIQNIRQ bit for an FIQ interrupt - * (by default, interrupts are mapped to IRQ and - * priority is 0 (highest). - */ - - for (i = 0; i < AM335x_IRC_IRQ_COUNT; ++i) - regs->ilr[i] = 0; - - /* 4 - Program the MIRn register: Enable interrupts (by default, - * all interrupt lines are masked). - */ - for (i = 0; i < 4; ++i) - regs->interrupts[i].mir_set = 0xFFFFFFFF; -} - -/** Get the currently active IRQ interrupt number - * - * @param regs Pointer to the irc memory mapped registers - * - * @return The active IRQ interrupt number - */ -static inline unsigned am335x_irc_inum_get(am335x_irc_regs_t *regs) -{ - return regs->sir_irq & AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK; -} - -/** Reset IRQ output and enable new IRQ generation - * - * @param regs Pointer to the irc memory mapped registers - */ -static inline void am335x_irc_irq_ack(am335x_irc_regs_t *regs) -{ - regs->control = AM335x_IRC_CONTROL_NEWIRQAGR_FLAG; -} - -/** Reset FIQ output and enable new FIQ generation - * - * @param regs Pointer to the irc memory mapped registers - */ -static inline void am335x_irc_fiq_ack(am335x_irc_regs_t *regs) -{ - regs->control = AM335x_IRC_CONTROL_NEWFIQAGR_FLAG; -} - -/** Clear an interrupt mask bit - * - * @param regs Pointer to the irc memory mapped registers - * @param inum The interrupt to be enabled - */ -static inline void am335x_irc_enable(am335x_irc_regs_t *regs, unsigned inum) -{ - ASSERT(inum < AM335x_IRC_IRQ_COUNT); - const unsigned set = inum / 32; - const unsigned pos = inum % 32; - regs->interrupts[set].mir_clear = (1 << pos); -} - -/** Set an interrupt mask bit - * - * @param regs Pointer to the irc memory mapped registers - * @param inum The interrupt to be disabled - */ -static inline void am335x_irc_disable(am335x_irc_regs_t *regs, unsigned inum) -{ - ASSERT(inum < AM335x_IRC_IRQ_COUNT); - const unsigned set = inum / 32; - const unsigned pos = inum % 32; - regs->interrupts[set].mir_set = (1 << pos); -} +#include #endif Index: kernel/genarch/include/genarch/drivers/amdm37x/gpt.h =================================================================== --- kernel/genarch/include/genarch/drivers/amdm37x/gpt.h (revision 820104d36ba9cd28a40e7a63571bf4eedbb7f2a1) +++ kernel/genarch/include/genarch/drivers/amdm37x/gpt.h (revision c2a698383608df44fde7e7cb4047a416d8688eee) @@ -39,4 +39,5 @@ #include #include +#include