- Timestamp:
- 2013-10-13T20:59:33Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 12d6c98
- Parents:
- 820104d (diff), 39bcc99 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - Location:
- boot
- Files:
-
- 1 added
- 9 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/Makefile.common
r820104d rc2a6983 112 112 $(USPACE_PATH)/srv/hid/remcons/remcons \ 113 113 $(USPACE_PATH)/srv/hid/isdv4_tablet/isdv4_tablet \ 114 $(USPACE_PATH)/srv/hid/rfb/rfb \ 115 $(USPACE_PATH)/srv/net/dhcp/dhcp \ 114 116 $(USPACE_PATH)/srv/net/dnsrsrv/dnsrsrv \ 115 117 $(USPACE_PATH)/srv/net/ethip/ethip \ 116 118 $(USPACE_PATH)/srv/net/inetsrv/inetsrv \ 117 119 $(USPACE_PATH)/srv/net/loopip/loopip \ 120 $(USPACE_PATH)/srv/net/nconfsrv/nconfsrv \ 118 121 $(USPACE_PATH)/srv/net/slip/slip \ 119 122 $(USPACE_PATH)/srv/net/tcp/tcp \ … … 121 124 $(USPACE_PATH)/srv/taskmon/taskmon 122 125 123 RD_DRVS = \ 124 infrastructure/root \ 126 RD_DRVS_ESSENTIAL = \ 127 infrastructure/root 128 129 RD_DRVS_NON_ESSENTIAL = \ 125 130 infrastructure/rootvirt \ 126 131 fb/kfb \ … … 163 168 $(USPACE_PATH)/app/blkdump/blkdump \ 164 169 $(USPACE_PATH)/app/bnchmark/bnchmark \ 170 $(USPACE_PATH)/app/corecfg/corecfg \ 165 171 $(USPACE_PATH)/app/devctl/devctl \ 166 172 $(USPACE_PATH)/app/dltest/dltest \ … … 169 175 $(USPACE_PATH)/app/dnscfg/dnscfg \ 170 176 $(USPACE_PATH)/app/dnsres/dnsres \ 177 $(USPACE_PATH)/app/download/download \ 171 178 $(USPACE_PATH)/app/edit/edit \ 172 179 $(USPACE_PATH)/app/inet/inet \ … … 174 181 $(USPACE_PATH)/app/killall/killall \ 175 182 $(USPACE_PATH)/app/loc/loc \ 183 $(USPACE_PATH)/app/mixerctl/mixerctl \ 176 184 $(USPACE_PATH)/app/logset/logset \ 177 185 $(USPACE_PATH)/app/mkfat/mkfat \ … … 191 199 $(USPACE_PATH)/app/nettest3/nettest3 \ 192 200 $(USPACE_PATH)/app/netecho/netecho \ 201 $(USPACE_PATH)/app/netspeed/netspeed \ 193 202 $(USPACE_PATH)/app/nterm/nterm \ 194 203 $(USPACE_PATH)/app/ping/ping \ 195 $(USPACE_PATH)/app/ping6/ping6 \196 204 $(USPACE_PATH)/app/stats/stats \ 197 205 $(USPACE_PATH)/app/sysinfo/sysinfo \ … … 202 210 $(USPACE_PATH)/app/websrv/websrv \ 203 211 $(USPACE_PATH)/app/date/date \ 204 $(USPACE_PATH)/app/vdemo/vdemo 212 $(USPACE_PATH)/app/vdemo/vdemo \ 213 $(USPACE_PATH)/app/viewer/viewer \ 214 $(USPACE_PATH)/app/df/df 205 215 206 216 ifeq ($(CONFIG_PCC),y) … … 237 247 RD_SRVS = $(RD_SRVS_ESSENTIAL) 238 248 RD_APPS = $(RD_APPS_ESSENTIAL) 249 RD_DRVS = $(RD_DRVS_ESSENTIAL) 239 250 else 240 251 RD_SRVS = $(RD_SRVS_ESSENTIAL) $(RD_SRVS_NON_ESSENTIAL) 241 252 RD_APPS = $(RD_APPS_ESSENTIAL) $(RD_APPS_NON_ESSENTIAL) 253 RD_DRVS = $(RD_DRVS_ESSENTIAL) $(RD_DRVS_NON_ESSENTIAL) 242 254 endif 243 255 -
boot/arch/amd64/Makefile.inc
r820104d rc2a6983 28 28 29 29 RD_SRVS_ESSENTIAL += \ 30 $(USPACE_PATH)/srv/audio/hound/hound \ 31 $(USPACE_PATH)/srv/devman/devman \ 30 32 $(USPACE_PATH)/srv/hw/irc/apic/apic \ 31 33 $(USPACE_PATH)/srv/hw/irc/i8259/i8259 32 34 33 RD_DRVS += \ 35 36 RD_DRVS_ESSENTIAL += \ 34 37 infrastructure/rootpc \ 35 38 block/ata_bd \ 36 39 bus/pci/pciintel \ 37 40 bus/isa \ 41 audio/sb16 \ 38 42 char/i8042 \ 43 char/ps2mouse \ 44 char/xtkbd 45 46 RD_DRVS_NON_ESSENTIAL += \ 39 47 char/ns8250 \ 40 char/ps2mouse \41 char/xtkbd \42 48 time/cmos-rtc \ 43 49 bus/usb/ehci\ … … 55 61 bus/isa 56 62 63 RD_APPS_ESSENTIAL += \ 64 $(USPACE_PATH)/app/edit/edit \ 65 $(USPACE_PATH)/app/mixerctl/mixerctl \ 66 $(USPACE_PATH)/app/wavplay/wavplay \ 67 57 68 BOOT_OUTPUT = $(ROOT_PATH)/image.iso 58 69 PREBUILD = $(INITRD).img -
boot/arch/arm32/Makefile.inc
r820104d rc2a6983 57 57 endif 58 58 59 RD_DRVS += \59 RD_DRVS_ESSENTIAL += \ 60 60 infrastructure/rootamdm37x \ 61 61 fb/amdm37x_dispc \ -
boot/arch/arm32/src/asm.S
r820104d rc2a6983 56 56 jump_to_kernel: 57 57 # 58 # TODO59 58 # Make sure that the I-cache, D-cache and memory are mutually coherent 60 59 # before passing control to the copied code. … … 68 67 #define CP15_C1_BP 11 69 68 #define CP15_C1_DC 2 70 # Disable I-cache and D-cache before the kernel is started. 69 70 71 #ifndef PROCESSOR_ARCH_armv7_a 71 72 mrc p15, 0, r4, c1, c0, 0 73 74 # D-cache before the kernel is started. 72 75 bic r4, r4, #(1 << CP15_C1_DC) 76 77 # Disable I-cache and Branche predictors. 73 78 bic r4, r4, #(1 << CP15_C1_IC) 74 79 bic r4, r4, #(1 << CP15_C1_BP) 80 75 81 mcr p15, 0, r4, c1, c0, 0 82 #endif 83 76 84 77 85 … … 81 89 #else 82 90 #cp15 dsb, r4 is ignored (should be zero) 91 mov r4, #0 83 92 mcr p15, 0, r4, c7, c10, 4 84 93 #endif 85 94 86 95 # Clean ICache and BPredictors, r4 ignored (SBZ) 96 mov r4, #0 87 97 mcr p15, 0, r4, c7, c5, 0 88 98 nop -
boot/arch/arm32/src/main.c
r820104d rc2a6983 53 53 extern void *bdata_end; 54 54 55 56 static inline void invalidate_icache(void)57 {58 /* ICIALLU Invalidate entire ICache */59 asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );60 }61 62 static inline void invalidate_dcache(void *address, size_t size)63 {64 const uintptr_t addr = (uintptr_t)address;65 /* DCIMVAC - invalidate by address to the point of coherence */66 for (uintptr_t a = addr; a < addr + size; a += 4) {67 asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );68 }69 }70 71 55 static inline void clean_dcache_poc(void *address, size_t size) 72 56 { 73 57 const uintptr_t addr = (uintptr_t)address; 74 /* DCCMVAC - clean by address to the point of coherence */75 58 for (uintptr_t a = addr; a < addr + size; a += 4) { 59 /* DCCMVAC - clean by address to the point of coherence */ 76 60 asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : ); 77 61 } … … 82 66 void bootstrap(void) 83 67 { 84 /* Make sure we run in memory code when caches are enabled,85 * make sure we read memory data too. This part is ARMv7 specific as86 * ARMv7 no longer invalidates caches on restart.87 * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/88 invalidate_icache();89 invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);90 91 68 /* Enable MMU and caches */ 92 69 mmu_start(); … … 105 82 components[i].start, components[i].name, components[i].inflated, 106 83 components[i].size); 107 invalidate_dcache(components[i].start, components[i].size);108 84 } 109 85 … … 148 124 halt(); 149 125 } 126 /* Make sure data are in the memory, ICache will need them */ 150 127 clean_dcache_poc(dest[i - 1], components[i - 1].inflated); 151 128 } -
boot/arch/arm32/src/mm.c
r820104d rc2a6983 37 37 #include <arch/asm.h> 38 38 #include <arch/mm.h> 39 #include <arch/cp15.h> 40 41 #ifdef PROCESSOR_ARCH_armv7_a 42 static unsigned log2(unsigned val) 43 { 44 unsigned log = 0; 45 while (val >> log++); 46 return log - 2; 47 } 48 49 static void dcache_invalidate_level(unsigned level) 50 { 51 CSSELR_write(level << 1); 52 const uint32_t ccsidr = CCSIDR_read(); 53 const unsigned sets = CCSIDR_SETS(ccsidr); 54 const unsigned ways = CCSIDR_WAYS(ccsidr); 55 const unsigned line_log = CCSIDR_LINESIZE_LOG(ccsidr); 56 const unsigned set_shift = line_log; 57 const unsigned way_shift = 32 - log2(ways); 58 59 for (unsigned k = 0; k < ways; ++k) 60 for (unsigned j = 0; j < sets; ++j) { 61 const uint32_t val = (level << 1) | 62 (j << set_shift) | (k << way_shift); 63 DCISW_write(val); 64 } 65 } 66 67 /** invalidate all dcaches -- armv7 */ 68 static void cache_invalidate(void) 69 { 70 const uint32_t cinfo = CLIDR_read(); 71 for (unsigned i = 0; i < 7; ++i) { 72 switch (CLIDR_CACHE(i, cinfo)) 73 { 74 case CLIDR_DCACHE_ONLY: 75 case CLIDR_SEP_CACHE: 76 case CLIDR_UNI_CACHE: 77 dcache_invalidate_level(i); 78 } 79 } 80 asm volatile ( "dsb\n" ); 81 ICIALLU_write(0); 82 asm volatile ( "isb\n" ); 83 } 84 #endif 39 85 40 86 /** Disable the MMU */ … … 60 106 static inline int section_cacheable(pfn_t section) 61 107 { 108 const unsigned long address = section << PTE_SECTION_SHIFT; 62 109 #ifdef MACHINE_gta02 63 unsigned long address = section << PTE_SECTION_SHIFT; 64 65 if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END) 66 return 0; 67 else 110 if (address < GTA02_IOMEM_START || address >= GTA02_IOMEM_END) 68 111 return 1; 69 112 #elif defined MACHINE_beagleboardxm 70 const unsigned long address = section << PTE_SECTION_SHIFT;71 113 if (address >= BBXM_RAM_START && address < BBXM_RAM_END) 72 114 return 1; 73 115 #elif defined MACHINE_beaglebone 74 const unsigned long address = section << PTE_SECTION_SHIFT;75 116 if (address >= AM335x_RAM_START && address < AM335x_RAM_END) 76 117 return 1; 77 118 #endif 78 return 0;119 return address * 0; 79 120 } 80 121 … … 95 136 { 96 137 pte->descriptor_type = PTE_DESCRIPTOR_SECTION; 97 pte->bufferable = 1;98 pte->cacheable = section_cacheable(frame);99 138 pte->xn = 0; 100 139 pte->domain = 0; 101 140 pte->should_be_zero_1 = 0; 102 141 pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW; 142 #ifdef PROCESSOR_ARCH_armv7_a 143 /* 144 * Keeps this setting in sync with memory type attributes in: 145 * init_boot_pt (boot/arch/arm32/src/mm.c) 146 * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) 147 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) 148 */ 149 pte->tex = section_cacheable(frame) ? 5 : 0; 150 pte->cacheable = section_cacheable(frame) ? 0 : 0; 151 pte->bufferable = section_cacheable(frame) ? 1 : 0; 152 #else 153 pte->bufferable = 1; 154 pte->cacheable = section_cacheable(frame); 103 155 pte->tex = 0; 156 #endif 104 157 pte->access_permission_1 = 0; 105 158 pte->shareable = 0; … … 113 166 static void init_boot_pt(void) 114 167 { 115 const pfn_t split_page = PTL0_ENTRIES; 116 /* Create 1:1 virtual-physical mapping (in lower 2 GB). */ 117 pfn_t page; 118 for (page = 0; page < split_page; page++) 168 /* 169 * Create 1:1 virtual-physical mapping. 170 * Physical memory on BBxM a BBone starts at 2GB 171 * boundary, icp has a memory mirror at 2GB. 172 * (ARM Integrator Core Module User guide ch. 6.3, p. 6-7) 173 * gta02 somehow works (probably due to limited address size), 174 * s3c2442b manual ch. 5, p.5-1: 175 * "Address space: 128Mbytes per bank (total 1GB/8 banks)" 176 */ 177 for (pfn_t page = 0; page < PTL0_ENTRIES; ++page) 119 178 init_ptl0_section(&boot_pt[page], page); 120 121 asm volatile ( 122 "mcr p15, 0, %[pt], c2, c0, 0\n" 123 :: [pt] "r" (boot_pt) 124 ); 179 180 /* 181 * Tell MMU page might be cached. Keeps this setting in sync 182 * with memory type attributes in: 183 * init_ptl0_section (boot/arch/arm32/src/mm.c) 184 * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) 185 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) 186 */ 187 uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK; 188 val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG; 189 TTBR0_write(val); 125 190 } 126 191 … … 141 206 * we disable caches before jumping to kernel 142 207 * so this is safe for all archs. 208 * Enable VMSAv6 the bit (23) is only writable on ARMv6. 209 * (and QEMU) 143 210 */ 211 #ifdef PROCESSOR_ARCH_armv6 212 "ldr r1, =0x00801805\n" 213 #else 144 214 "ldr r1, =0x00001805\n" 215 #endif 145 216 146 217 "orr r0, r0, r1\n" … … 160 231 void mmu_start() { 161 232 disable_paging(); 233 #ifdef PROCESSOR_ARCH_armv7_a 234 /* Make sure we run in memory code when caches are enabled, 235 * make sure we read memory data too. This part is ARMv7 specific as 236 * ARMv7 no longer invalidates caches on restart. 237 * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/ 238 cache_invalidate(); 239 #endif 162 240 init_boot_pt(); 163 241 enable_paging(); -
boot/arch/mips32/Makefile.inc
r820104d rc2a6983 50 50 endif 51 51 52 ifeq ($(MACHINE), $(filter $(MACHINE),bmalta lmalta)) 53 RD_DRVS_ESSENTIAL += \ 54 infrastructure/rootmalta \ 55 block/ata_bd \ 56 bus/pci/pciintel \ 57 bus/isa \ 58 char/i8042 \ 59 char/ps2mouse \ 60 char/xtkbd 61 62 RD_DRV_CFG += \ 63 bus/isa 64 endif 52 65 53 66 SOURCES = \ -
boot/arch/ppc32/Makefile.inc
r820104d rc2a6983 42 42 $(USPACE_PATH)/srv/hw/bus/cuda_adb/cuda_adb 43 43 44 RD_DRVS += \44 RD_DRVS_ESSENTIAL += \ 45 45 infrastructure/rootmac \ 46 46 bus/pci/pciintel \ -
boot/arch/sparc64/src/asm.S
r820104d rc2a6983 30 30 #include <arch/arch.h> 31 31 32 #if defined(PROCESSOR_us) || defined(PROCESSOR_us3) 32 33 #define ICACHE_SIZE 8192 33 34 #define ICACHE_LINE_SIZE 32 34 35 #define ICACHE_SET_BIT (1 << 13) 35 36 #define ASI_ICACHE_TAG 0x67 37 #endif /* PROCESSOR_us || PROCESSOR_us3 */ 36 38 37 39 .register %g2, #scratch … … 134 136 # Flush I-cache 135 137 icache_flush: 138 #if defined(PROCESSOR_us) || defined(PROCESSOR_us3) 136 139 set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 137 140 stxa %g0, [%g1] ASI_ICACHE_TAG … … 149 152 150 153 nop 154 #else 155 // TODO: sun4v 156 retl 157 nop 158 #endif /* PROCESSOR_us || PROCESSOR_us3 */ 151 159 152 160 .global ofw
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