Changeset c2a6983 in mainline for boot


Ignore:
Timestamp:
2013-10-13T20:59:33Z (12 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
12d6c98
Parents:
820104d (diff), 39bcc99 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes

Location:
boot
Files:
1 added
9 edited

Legend:

Unmodified
Added
Removed
  • boot/Makefile.common

    r820104d rc2a6983  
    112112        $(USPACE_PATH)/srv/hid/remcons/remcons \
    113113        $(USPACE_PATH)/srv/hid/isdv4_tablet/isdv4_tablet \
     114        $(USPACE_PATH)/srv/hid/rfb/rfb \
     115        $(USPACE_PATH)/srv/net/dhcp/dhcp \
    114116        $(USPACE_PATH)/srv/net/dnsrsrv/dnsrsrv \
    115117        $(USPACE_PATH)/srv/net/ethip/ethip \
    116118        $(USPACE_PATH)/srv/net/inetsrv/inetsrv \
    117119        $(USPACE_PATH)/srv/net/loopip/loopip \
     120        $(USPACE_PATH)/srv/net/nconfsrv/nconfsrv \
    118121        $(USPACE_PATH)/srv/net/slip/slip \
    119122        $(USPACE_PATH)/srv/net/tcp/tcp \
     
    121124        $(USPACE_PATH)/srv/taskmon/taskmon
    122125
    123 RD_DRVS = \
    124         infrastructure/root \
     126RD_DRVS_ESSENTIAL = \
     127        infrastructure/root
     128
     129RD_DRVS_NON_ESSENTIAL = \
    125130        infrastructure/rootvirt \
    126131        fb/kfb \
     
    163168        $(USPACE_PATH)/app/blkdump/blkdump \
    164169        $(USPACE_PATH)/app/bnchmark/bnchmark \
     170        $(USPACE_PATH)/app/corecfg/corecfg \
    165171        $(USPACE_PATH)/app/devctl/devctl \
    166172        $(USPACE_PATH)/app/dltest/dltest \
     
    169175        $(USPACE_PATH)/app/dnscfg/dnscfg \
    170176        $(USPACE_PATH)/app/dnsres/dnsres \
     177        $(USPACE_PATH)/app/download/download \
    171178        $(USPACE_PATH)/app/edit/edit \
    172179        $(USPACE_PATH)/app/inet/inet \
     
    174181        $(USPACE_PATH)/app/killall/killall \
    175182        $(USPACE_PATH)/app/loc/loc \
     183        $(USPACE_PATH)/app/mixerctl/mixerctl \
    176184        $(USPACE_PATH)/app/logset/logset \
    177185        $(USPACE_PATH)/app/mkfat/mkfat \
     
    191199        $(USPACE_PATH)/app/nettest3/nettest3 \
    192200        $(USPACE_PATH)/app/netecho/netecho \
     201        $(USPACE_PATH)/app/netspeed/netspeed \
    193202        $(USPACE_PATH)/app/nterm/nterm \
    194203        $(USPACE_PATH)/app/ping/ping \
    195         $(USPACE_PATH)/app/ping6/ping6 \
    196204        $(USPACE_PATH)/app/stats/stats \
    197205        $(USPACE_PATH)/app/sysinfo/sysinfo \
     
    202210        $(USPACE_PATH)/app/websrv/websrv \
    203211        $(USPACE_PATH)/app/date/date \
    204         $(USPACE_PATH)/app/vdemo/vdemo
     212        $(USPACE_PATH)/app/vdemo/vdemo \
     213        $(USPACE_PATH)/app/viewer/viewer \
     214        $(USPACE_PATH)/app/df/df
    205215
    206216ifeq ($(CONFIG_PCC),y)
     
    237247RD_SRVS = $(RD_SRVS_ESSENTIAL)
    238248RD_APPS = $(RD_APPS_ESSENTIAL)
     249RD_DRVS = $(RD_DRVS_ESSENTIAL)
    239250else
    240251RD_SRVS = $(RD_SRVS_ESSENTIAL) $(RD_SRVS_NON_ESSENTIAL)
    241252RD_APPS = $(RD_APPS_ESSENTIAL) $(RD_APPS_NON_ESSENTIAL)
     253RD_DRVS = $(RD_DRVS_ESSENTIAL) $(RD_DRVS_NON_ESSENTIAL)
    242254endif
    243255
  • boot/arch/amd64/Makefile.inc

    r820104d rc2a6983  
    2828
    2929RD_SRVS_ESSENTIAL += \
     30        $(USPACE_PATH)/srv/audio/hound/hound \
     31        $(USPACE_PATH)/srv/devman/devman \
    3032        $(USPACE_PATH)/srv/hw/irc/apic/apic \
    3133        $(USPACE_PATH)/srv/hw/irc/i8259/i8259
    3234
    33 RD_DRVS += \
     35
     36RD_DRVS_ESSENTIAL += \
    3437        infrastructure/rootpc \
    3538        block/ata_bd \
    3639        bus/pci/pciintel \
    3740        bus/isa \
     41        audio/sb16 \
    3842        char/i8042 \
     43        char/ps2mouse \
     44        char/xtkbd
     45
     46RD_DRVS_NON_ESSENTIAL += \
    3947        char/ns8250 \
    40         char/ps2mouse \
    41         char/xtkbd \
    4248        time/cmos-rtc \
    4349        bus/usb/ehci\
     
    5561        bus/isa
    5662
     63RD_APPS_ESSENTIAL += \
     64        $(USPACE_PATH)/app/edit/edit \
     65        $(USPACE_PATH)/app/mixerctl/mixerctl \
     66        $(USPACE_PATH)/app/wavplay/wavplay \
     67       
    5768BOOT_OUTPUT = $(ROOT_PATH)/image.iso
    5869PREBUILD = $(INITRD).img
  • boot/arch/arm32/Makefile.inc

    r820104d rc2a6983  
    5757endif
    5858
    59 RD_DRVS += \
     59RD_DRVS_ESSENTIAL += \
    6060        infrastructure/rootamdm37x \
    6161        fb/amdm37x_dispc \
  • boot/arch/arm32/src/asm.S

    r820104d rc2a6983  
    5656jump_to_kernel:
    5757        #
    58         # TODO
    5958        # Make sure that the I-cache, D-cache and memory are mutually coherent
    6059        # before passing control to the copied code.
     
    6867#define CP15_C1_BP              11
    6968#define CP15_C1_DC              2
    70         # Disable I-cache and D-cache before the kernel is started.
     69
     70
     71#ifndef PROCESSOR_ARCH_armv7_a
    7172        mrc     p15, 0, r4, c1, c0, 0
     73       
     74        # D-cache before the kernel is started.
    7275        bic     r4, r4, #(1 << CP15_C1_DC)
     76
     77        # Disable I-cache and Branche predictors.
    7378        bic     r4, r4, #(1 << CP15_C1_IC)
    7479        bic     r4, r4, #(1 << CP15_C1_BP)
     80       
    7581        mcr     p15, 0, r4, c1, c0, 0
     82#endif
     83
    7684
    7785       
     
    8189#else
    8290        #cp15 dsb, r4 is ignored (should be zero)
     91        mov r4, #0
    8392        mcr p15, 0, r4, c7, c10, 4
    8493#endif
    8594       
    8695        # Clean ICache and BPredictors, r4 ignored (SBZ)
     96        mov r4, #0
    8797        mcr p15, 0, r4, c7, c5, 0
    8898        nop
  • boot/arch/arm32/src/main.c

    r820104d rc2a6983  
    5353extern void *bdata_end;
    5454
    55 
    56 static inline void invalidate_icache(void)
    57 {
    58         /* ICIALLU Invalidate entire ICache */
    59         asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
    60 }
    61 
    62 static inline void invalidate_dcache(void *address, size_t size)
    63 {
    64         const uintptr_t addr = (uintptr_t)address;
    65         /* DCIMVAC - invalidate by address to the point of coherence */
    66         for (uintptr_t a = addr; a < addr + size; a += 4) {
    67                 asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
    68         }
    69 }
    70 
    7155static inline void clean_dcache_poc(void *address, size_t size)
    7256{
    7357        const uintptr_t addr = (uintptr_t)address;
    74         /* DCCMVAC - clean by address to the point of coherence */
    7558        for (uintptr_t a = addr; a < addr + size; a += 4) {
     59                /* DCCMVAC - clean by address to the point of coherence */
    7660                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
    7761        }
     
    8266void bootstrap(void)
    8367{
    84         /* Make sure  we run in memory code when caches are enabled,
    85          * make sure we read memory data too. This part is ARMv7 specific as
    86          * ARMv7 no longer invalidates caches on restart.
    87          * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
    88         invalidate_icache();
    89         invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
    90 
    9168        /* Enable MMU and caches */
    9269        mmu_start();
     
    10582                    components[i].start, components[i].name, components[i].inflated,
    10683                    components[i].size);
    107                 invalidate_dcache(components[i].start, components[i].size);
    10884        }
    10985       
     
    148124                        halt();
    149125                }
     126                /* Make sure data are in the memory, ICache will need them */
    150127                clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
    151128        }
  • boot/arch/arm32/src/mm.c

    r820104d rc2a6983  
    3737#include <arch/asm.h>
    3838#include <arch/mm.h>
     39#include <arch/cp15.h>
     40
     41#ifdef PROCESSOR_ARCH_armv7_a
     42static unsigned log2(unsigned val)
     43{
     44        unsigned log = 0;
     45        while (val >> log++);
     46        return log - 2;
     47}
     48
     49static void dcache_invalidate_level(unsigned level)
     50{
     51        CSSELR_write(level << 1);
     52        const uint32_t ccsidr = CCSIDR_read();
     53        const unsigned sets = CCSIDR_SETS(ccsidr);
     54        const unsigned ways = CCSIDR_WAYS(ccsidr);
     55        const unsigned line_log = CCSIDR_LINESIZE_LOG(ccsidr);
     56        const unsigned set_shift = line_log;
     57        const unsigned way_shift = 32 - log2(ways);
     58
     59        for (unsigned k = 0; k < ways; ++k)
     60                for (unsigned j = 0; j < sets; ++j) {
     61                        const uint32_t val = (level << 1) |
     62                            (j << set_shift) | (k << way_shift);
     63                        DCISW_write(val);
     64                }
     65}
     66
     67/** invalidate all dcaches -- armv7 */
     68static void cache_invalidate(void)
     69{
     70        const uint32_t cinfo = CLIDR_read();
     71        for (unsigned i = 0; i < 7; ++i) {
     72                switch (CLIDR_CACHE(i, cinfo))
     73                {
     74                case CLIDR_DCACHE_ONLY:
     75                case CLIDR_SEP_CACHE:
     76                case CLIDR_UNI_CACHE:
     77                        dcache_invalidate_level(i);
     78                }
     79        }
     80        asm volatile ( "dsb\n" );
     81        ICIALLU_write(0);
     82        asm volatile ( "isb\n" );
     83}
     84#endif
    3985
    4086/** Disable the MMU */
     
    60106static inline int section_cacheable(pfn_t section)
    61107{
     108        const unsigned long address = section << PTE_SECTION_SHIFT;
    62109#ifdef MACHINE_gta02
    63         unsigned long address = section << PTE_SECTION_SHIFT;
    64 
    65         if (address >= GTA02_IOMEM_START && address < GTA02_IOMEM_END)
    66                 return 0;
    67         else
     110        if (address < GTA02_IOMEM_START || address >= GTA02_IOMEM_END)
    68111                return 1;
    69112#elif defined MACHINE_beagleboardxm
    70         const unsigned long address = section << PTE_SECTION_SHIFT;
    71113        if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
    72114                return 1;
    73115#elif defined MACHINE_beaglebone
    74         const unsigned long address = section << PTE_SECTION_SHIFT;
    75116        if (address >= AM335x_RAM_START && address < AM335x_RAM_END)
    76117                return 1;
    77118#endif
    78         return 0;
     119        return address * 0;
    79120}
    80121
     
    95136{
    96137        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    97         pte->bufferable = 1;
    98         pte->cacheable = section_cacheable(frame);
    99138        pte->xn = 0;
    100139        pte->domain = 0;
    101140        pte->should_be_zero_1 = 0;
    102141        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
     142#ifdef PROCESSOR_ARCH_armv7_a
     143        /*
     144         * Keeps this setting in sync with memory type attributes in:
     145         * init_boot_pt (boot/arch/arm32/src/mm.c)
     146         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
     147         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
     148         */
     149        pte->tex = section_cacheable(frame) ? 5 : 0;
     150        pte->cacheable = section_cacheable(frame) ? 0 : 0;
     151        pte->bufferable = section_cacheable(frame) ? 1 : 0;
     152#else
     153        pte->bufferable = 1;
     154        pte->cacheable = section_cacheable(frame);
    103155        pte->tex = 0;
     156#endif
    104157        pte->access_permission_1 = 0;
    105158        pte->shareable = 0;
     
    113166static void init_boot_pt(void)
    114167{
    115         const pfn_t split_page = PTL0_ENTRIES;
    116         /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    117         pfn_t page;
    118         for (page = 0; page < split_page; page++)
     168        /*
     169         * Create 1:1 virtual-physical mapping.
     170         * Physical memory on BBxM a BBone starts at 2GB
     171         * boundary, icp has a memory mirror at 2GB.
     172         * (ARM Integrator Core Module User guide ch. 6.3,  p. 6-7)
     173         * gta02 somehow works (probably due to limited address size),
     174         * s3c2442b manual ch. 5, p.5-1:
     175         * "Address space: 128Mbytes per bank (total 1GB/8 banks)"
     176         */
     177        for (pfn_t page = 0; page < PTL0_ENTRIES; ++page)
    119178                init_ptl0_section(&boot_pt[page], page);
    120        
    121         asm volatile (
    122                 "mcr p15, 0, %[pt], c2, c0, 0\n"
    123                 :: [pt] "r" (boot_pt)
    124         );
     179
     180        /*
     181         * Tell MMU page might be cached. Keeps this setting in sync
     182         * with memory type attributes in:
     183         * init_ptl0_section (boot/arch/arm32/src/mm.c)
     184         * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
     185         * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
     186         */
     187        uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
     188        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
     189        TTBR0_write(val);
    125190}
    126191
     
    141206                 * we disable caches before jumping to kernel
    142207                 * so this is safe for all archs.
     208                 * Enable VMSAv6 the bit (23) is only writable on ARMv6.
     209                 * (and QEMU)
    143210                 */
     211#ifdef PROCESSOR_ARCH_armv6
     212                "ldr r1, =0x00801805\n"
     213#else
    144214                "ldr r1, =0x00001805\n"
     215#endif
    145216               
    146217                "orr r0, r0, r1\n"
     
    160231void mmu_start() {
    161232        disable_paging();
     233#ifdef PROCESSOR_ARCH_armv7_a
     234        /* Make sure we run in memory code when caches are enabled,
     235         * make sure we read memory data too. This part is ARMv7 specific as
     236         * ARMv7 no longer invalidates caches on restart.
     237         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
     238        cache_invalidate();
     239#endif
    162240        init_boot_pt();
    163241        enable_paging();
  • boot/arch/mips32/Makefile.inc

    r820104d rc2a6983  
    5050endif
    5151
     52ifeq ($(MACHINE), $(filter $(MACHINE),bmalta lmalta))
     53        RD_DRVS_ESSENTIAL += \
     54                infrastructure/rootmalta \
     55                block/ata_bd \
     56                bus/pci/pciintel \
     57                bus/isa \
     58                char/i8042 \
     59                char/ps2mouse \
     60                char/xtkbd
     61
     62        RD_DRV_CFG += \
     63                bus/isa
     64endif
    5265
    5366SOURCES = \
  • boot/arch/ppc32/Makefile.inc

    r820104d rc2a6983  
    4242        $(USPACE_PATH)/srv/hw/bus/cuda_adb/cuda_adb
    4343
    44 RD_DRVS += \
     44RD_DRVS_ESSENTIAL += \
    4545        infrastructure/rootmac \
    4646        bus/pci/pciintel \
  • boot/arch/sparc64/src/asm.S

    r820104d rc2a6983  
    3030#include <arch/arch.h>
    3131
     32#if defined(PROCESSOR_us) || defined(PROCESSOR_us3)
    3233#define ICACHE_SIZE       8192
    3334#define ICACHE_LINE_SIZE  32
    3435#define ICACHE_SET_BIT    (1 << 13)
    3536#define ASI_ICACHE_TAG    0x67
     37#endif  /* PROCESSOR_us || PROCESSOR_us3 */
    3638
    3739.register %g2, #scratch
     
    134136# Flush I-cache
    135137icache_flush:
     138#if defined(PROCESSOR_us) || defined(PROCESSOR_us3)
    136139        set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
    137140        stxa %g0, [%g1] ASI_ICACHE_TAG
     
    149152       
    150153        nop
     154#else
     155        // TODO: sun4v
     156        retl
     157        nop
     158#endif  /* PROCESSOR_us || PROCESSOR_us3 */
    151159
    152160.global ofw
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