Changeset c03ee1c in mainline for kernel/arch/ia32/include/mm
- Timestamp:
- 2007-06-13T17:49:57Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- de7663f
- Parents:
- 6b781c0
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia32/include/mm/page.h
r6b781c0 rc03ee1c 57 57 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out. 58 58 */ 59 60 /* Number of entries in each level. */ 59 61 #define PTL0_ENTRIES_ARCH 1024 60 62 #define PTL1_ENTRIES_ARCH 0 … … 62 64 #define PTL3_ENTRIES_ARCH 1024 63 65 64 #define PTL0_SIZE_ARCH ONE_FRAME 65 #define PTL1_SIZE_ARCH 0 66 #define PTL2_SIZE_ARCH 0 67 #define PTL3_SIZE_ARCH ONE_FRAME 66 /* Page table sizes for each level. */ 67 #define PTL0_SIZE_ARCH ONE_FRAME 68 #define PTL1_SIZE_ARCH 0 69 #define PTL2_SIZE_ARCH 0 70 #define PTL3_SIZE_ARCH ONE_FRAME 68 71 72 /* Macros calculating indices for each level. */ 69 73 #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) 70 74 #define PTL1_INDEX_ARCH(vaddr) 0 … … 72 76 #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff) 73 77 74 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address) << 12)) 75 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) 76 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) 77 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)((((pte_t *)(ptl3))[(i)].frame_address) << 12)) 78 /* Get PTE address accessors for each level. */ 79 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ 80 ((pte_t *) ((((pte_t *) (ptl0))[(i)].frame_address) << 12)) 81 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ 82 (ptl1) 83 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ 84 (ptl2) 85 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ 86 ((uintptr_t) ((((pte_t *) (ptl3))[(i)].frame_address) << 12)) 78 87 79 #define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((uintptr_t) (ptl0))) 80 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].frame_address = (a)>>12) 88 /* Set PTE address accessors for each level. */ 89 #define SET_PTL0_ADDRESS_ARCH(ptl0) \ 90 (write_cr3((uintptr_t) (ptl0))) 91 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ 92 (((pte_t *) (ptl0))[(i)].frame_address = (a) >> 12) 81 93 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) 82 94 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) 83 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].frame_address = (a)>>12) 95 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ 96 (((pte_t *) (ptl3))[(i)].frame_address = (a) >> 12) 84 97 85 #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) 86 #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT 87 #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT 88 #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) 98 /* Get PTE flags accessors for each level. */ 99 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ 100 get_pt_flags((pte_t *) (ptl0), (index_t) (i)) 101 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ 102 PAGE_PRESENT 103 #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ 104 PAGE_PRESENT 105 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ 106 get_pt_flags((pte_t *) (ptl3), (index_t) (i)) 89 107 90 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) 108 /* Set PTE flags accessors for each level. */ 109 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ 110 set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) 91 111 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) 92 112 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) 93 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) 113 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ 114 set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) 94 115 95 #define PTE_VALID_ARCH(p) (*((uint32_t *) (p)) != 0) 96 #define PTE_PRESENT_ARCH(p) ((p)->present != 0) 97 #define PTE_GET_FRAME_ARCH(p) ((p)->frame_address << FRAME_WIDTH) 98 #define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0) 116 /* Macros for querying the last level entries. */ 117 #define PTE_VALID_ARCH(p) \ 118 (*((uint32_t *) (p)) != 0) 119 #define PTE_PRESENT_ARCH(p) \ 120 ((p)->present != 0) 121 #define PTE_GET_FRAME_ARCH(p) \ 122 ((p)->frame_address << FRAME_WIDTH) 123 #define PTE_WRITABLE_ARCH(p) \ 124 ((p)->writeable != 0) 99 125 #define PTE_EXECUTABLE_ARCH(p) 1 100 126 … … 106 132 /* Page fault error codes. */ 107 133 108 /** When bit on this position is 0, the page fault was caused by a not-present page. */ 134 /** When bit on this position is 0, the page fault was caused by a not-present 135 * page. 136 */ 109 137 #define PFERR_CODE_P (1 << 0) 110 138 … … 122 150 pte_t *p = &pt[i]; 123 151 124 return ( 125 (!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | 126 (!p->present) << PAGE_PRESENT_SHIFT | 127 p->uaccessible << PAGE_USER_SHIFT | 128 1<<PAGE_READ_SHIFT | 129 p->writeable << PAGE_WRITE_SHIFT | 130 1<<PAGE_EXEC_SHIFT | 131 p->global << PAGE_GLOBAL_SHIFT 132 ); 152 return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT | 153 (!p->present) << PAGE_PRESENT_SHIFT | 154 p->uaccessible << PAGE_USER_SHIFT | 155 1 << PAGE_READ_SHIFT | 156 p->writeable << PAGE_WRITE_SHIFT | 157 1 << PAGE_EXEC_SHIFT | 158 p->global << PAGE_GLOBAL_SHIFT); 133 159 } 134 160 … … 144 170 145 171 /* 146 * Ensure that there is at least one bit set even if the present bit is cleared. 172 * Ensure that there is at least one bit set even if the present bit is 173 * cleared. 147 174 */ 148 175 p->soft_valid = true;
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