Changeset bd48f4c in mainline for kernel/arch/arm32


Ignore:
Timestamp:
2010-07-12T10:53:30Z (15 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bd11d3e
Parents:
c40e6ef (diff), bee2d4c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/arm32
Files:
14 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/Makefile.inc

    rc40e6ef rbd48f4c  
    4646        arch/$(KARCH)/src/context.S \
    4747        arch/$(KARCH)/src/dummy.S \
    48         arch/$(KARCH)/src/panic.S \
    4948        arch/$(KARCH)/src/cpu/cpu.c \
    5049        arch/$(KARCH)/src/ddi/ddi.c \

  • kernel/arch/arm32/include/asm.h

    rc40e6ef rbd48f4c  
    4141#include <config.h>
    4242#include <arch/interrupt.h>
     43#include <trace.h>
    4344
    4445/** No such instruction on ARM to sleep CPU. */
    45 static inline void cpu_sleep(void)
     46NO_TRACE static inline void cpu_sleep(void)
    4647{
    4748}
    4849
    49 static inline void pio_write_8(ioport8_t *port, uint8_t v)
     50NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
    5051{
    5152        *port = v;
    5253}
    5354
    54 static inline void pio_write_16(ioport16_t *port, uint16_t v)
     55NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
    5556{
    5657        *port = v;
    5758}
    5859
    59 static inline void pio_write_32(ioport32_t *port, uint32_t v)
     60NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
    6061{
    6162        *port = v;
    6263}
    6364
    64 static inline uint8_t pio_read_8(ioport8_t *port)
     65NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    6566{
    6667        return *port;
    6768}
    6869
    69 static inline uint16_t pio_read_16(ioport16_t *port)
     70NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    7071{
    7172        return *port;
    7273}
    7374
    74 static inline uint32_t pio_read_32(ioport32_t *port)
     75NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    7576{
    7677        return *port;
    … …  
    8485 *
    8586 */
    86 static inline uintptr_t get_stack_base(void)
     87NO_TRACE static inline uintptr_t get_stack_base(void)
    8788{
    8889        uintptr_t v;
     90       
    8991        asm volatile (
    9092                "and %[v], sp, %[size]\n"
    … …  
    9294                : [size] "r" (~(STACK_SIZE - 1))
    9395        );
     96       
    9497        return v;
    9598}

  • kernel/arch/arm32/include/atomic.h

    rc40e6ef rbd48f4c  
    3838
    3939#include <arch/asm.h>
     40#include <trace.h>
    4041
    4142/** Atomic addition.
    … …  
    4748 *
    4849 */
    49 static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i)
     50NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val,
     51    atomic_count_t i)
    5052{
    5153        /*
    … …  
    6668 *
    6769 */
    68 static inline void atomic_inc(atomic_t *val)
     70NO_TRACE static inline void atomic_inc(atomic_t *val)
    6971{
    7072        atomic_add(val, 1);
    … …  
    7678 *
    7779 */
    78 static inline void atomic_dec(atomic_t *val) {
     80NO_TRACE static inline void atomic_dec(atomic_t *val) {
    7981        atomic_add(val, -1);
    8082}
    … …  
    8688 *
    8789 */
    88 static inline atomic_count_t atomic_preinc(atomic_t *val)
     90NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val)
    8991{
    9092        return atomic_add(val, 1);
    … …  
    9799 *
    98100 */
    99 static inline atomic_count_t atomic_predec(atomic_t *val)
     101NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val)
    100102{
    101103        return atomic_add(val, -1);
    … …  
    108110 *
    109111 */
    110 static inline atomic_count_t atomic_postinc(atomic_t *val)
     112NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    111113{
    112114        return atomic_add(val, 1) - 1;
    … …  
    119121 *
    120122 */
    121 static inline atomic_count_t atomic_postdec(atomic_t *val)
     123NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    122124{
    123125        return atomic_add(val, -1) + 1;

  • kernel/arch/arm32/include/cycle.h

    rc40e6ef rbd48f4c  
    3737#define KERN_arm32_CYCLE_H_
    3838
    39 /** Returns count of CPU cycles.
     39#include <trace.h>
     40
     41/** Return count of CPU cycles.
    4042 *
    41  *  No such instruction on ARM to get count of cycles.
     43 * No such instruction on ARM to get count of cycles.
    4244 *
    43  *  @return Count of CPU cycles.
     45 * @return Count of CPU cycles.
     46 *
    4447 */
    45 static inline uint64_t get_cycle(void)
     48NO_TRACE static inline uint64_t get_cycle(void)
    4649{
    4750        return 0;

  • kernel/arch/arm32/include/exception.h

    rc40e6ef rbd48f4c  
    2828 */
    2929
    30 /** @addtogroup arm32   
     30/** @addtogroup arm32
    3131 * @{
    3232 */
    … …  
    4040#include <typedefs.h>
    4141#include <arch/regutils.h>
     42#include <trace.h>
    4243
    4344/** If defined, forces using of high exception vectors. */
    … …  
    4546
    4647#ifdef HIGH_EXCEPTION_VECTORS
    47         #define EXC_BASE_ADDRESS        0xffff0000
     48        #define EXC_BASE_ADDRESS  0xffff0000
    4849#else
    49         #define EXC_BASE_ADDRESS        0x0
     50        #define EXC_BASE_ADDRESS  0x0
    5051#endif
    5152
    5253/* Exception Vectors */
    53 #define EXC_RESET_VEC          (EXC_BASE_ADDRESS + 0x0)
    54 #define EXC_UNDEF_INSTR_VEC    (EXC_BASE_ADDRESS + 0x4)
    55 #define EXC_SWI_VEC            (EXC_BASE_ADDRESS + 0x8)
    56 #define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc)
    57 #define EXC_DATA_ABORT_VEC     (EXC_BASE_ADDRESS + 0x10)
    58 #define EXC_IRQ_VEC            (EXC_BASE_ADDRESS + 0x18)
    59 #define EXC_FIQ_VEC            (EXC_BASE_ADDRESS + 0x1c)
     54#define EXC_RESET_VEC           (EXC_BASE_ADDRESS + 0x0)
     55#define EXC_UNDEF_INSTR_VEC     (EXC_BASE_ADDRESS + 0x4)
     56#define EXC_SWI_VEC             (EXC_BASE_ADDRESS + 0x8)
     57#define EXC_PREFETCH_ABORT_VEC  (EXC_BASE_ADDRESS + 0xc)
     58#define EXC_DATA_ABORT_VEC      (EXC_BASE_ADDRESS + 0x10)
     59#define EXC_IRQ_VEC             (EXC_BASE_ADDRESS + 0x18)
     60#define EXC_FIQ_VEC             (EXC_BASE_ADDRESS + 0x1c)
    6061
    6162/* Exception numbers */
    … …  
    6869#define EXC_FIQ             6
    6970
    70 
    7171/** Kernel stack pointer.
    7272 *
    7373 * It is set when thread switches to user mode,
    7474 * and then used for exception handling.
     75 *
    7576 */
    7677extern uintptr_t supervisor_sp;
    77 
    7878
    7979/** Temporary exception stack pointer.
    … …  
    8181 * Temporary stack is used in exceptions handling routines
    8282 * before switching to thread's kernel stack.
     83 *
    8384 */
    8485extern uintptr_t exc_stack;
    85 
    8686
    8787/** Struct representing CPU state saved when an exception occurs. */
    … …  
    9090        uint32_t sp;
    9191        uint32_t lr;
    92 
     92       
    9393        uint32_t r0;
    9494        uint32_t r1;
    … …  
    104104        uint32_t fp;
    105105        uint32_t r12;
    106 
     106       
    107107        uint32_t pc;
    108108} istate_t;
    109109
    110 
    111 /** Sets Program Counter member of given istate structure.
     110/** Set Program Counter member of given istate structure.
    112111 *
    113  * @param istate istate structure
     112 * @param istate  istate structure
    114113 * @param retaddr new value of istate's PC member
     114 *
    115115 */
    116 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
     116NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     117    uintptr_t retaddr)
    117118{
    118         istate->pc = retaddr;
     119        istate->pc = retaddr;
    119120}
    120121
    121 
    122 /** Returns true if exception happened while in userspace. */
    123 static inline int istate_from_uspace(istate_t *istate)
     122/** Return true if exception happened while in userspace. */
     123NO_TRACE static inline int istate_from_uspace(istate_t *istate)
    124124{
    125         return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
     125        return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
    126126}
    127127
    128 
    129 /** Returns Program Counter member of given istate structure. */
    130 static inline unative_t istate_get_pc(istate_t *istate)
     128/** Return Program Counter member of given istate structure. */
     129NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
    131130{
    132         return istate->pc;
     131        return istate->pc;
    133132}
    134133
    135 static inline unative_t istate_get_fp(istate_t *istate)
     134NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
    136135{
    137136        return istate->fp;
    138137}
    139138
    140 
    141139extern void install_exception_handlers(void);
    142140extern void exception_init(void);
    143 extern void print_istate(istate_t *istate);
    144141extern void reset_exception_entry(void);
    145142extern void irq_exception_entry(void);
    … …  
    150147extern void swi_exception_entry(void);
    151148
    152 
    153149#endif
    154150

  • kernel/arch/arm32/include/faddr.h

    rc40e6ef rbd48f4c  
    2727 */
    2828
    29 /** @addtogroup arm32   
     29/** @addtogroup arm32
    3030 * @{
    3131 */
    … …  
    4242 *
    4343 * @param fptr Function pointer.
     44 *
    4445 */
    45 #define FADDR(fptr)             ((uintptr_t) (fptr))
     46#define FADDR(fptr)  ((uintptr_t) (fptr))
    4647
    4748#endif

  • kernel/arch/arm32/include/interrupt.h

    rc40e6ef rbd48f4c  
    4141
    4242/** Initial size of exception dispatch table. */
    43 #define IVT_ITEMS       6
     43#define IVT_ITEMS  6
    4444
    4545/** Index of the first item in exception dispatch table. */
    46 #define IVT_FIRST       0
    47 
     46#define IVT_FIRST  0
    4847
    4948extern void interrupt_init(void);
    … …  
    5453extern bool interrupts_disabled(void);
    5554
    56 
    5755#endif
    5856

  • kernel/arch/arm32/include/mm/page.h

    rc40e6ef rbd48f4c  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */
    … …  
    4040#include <mm/mm.h>
    4141#include <arch/exception.h>
     42#include <trace.h>
    4243
    4344#define PAGE_WIDTH      FRAME_WIDTH
    … …  
    192193/** Sets the address of level 0 page table.
    193194 *
    194  * @param pt    Pointer to the page table to set.
    195  */   
    196 static inline void set_ptl0_addr(pte_t *pt)
     195 * @param pt Pointer to the page table to set.
     196 *
     197 */
     198NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
    197199{
    198200        asm volatile (
    … …  
    205207/** Returns level 0 page table entry flags.
    206208 *
    207  *  @param pt     Level 0 page table.
    208  *  @param i      Index of the entry to return.
    209  */
    210 static inline int get_pt_level0_flags(pte_t *pt, size_t i)
     209 * @param pt Level 0 page table.
     210 * @param i  Index of the entry to return.
     211 *
     212 */
     213NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
    211214{
    212215        pte_level0_t *p = &pt[i].l0;
    213216        int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT);
    214 
     217       
    215218        return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) |
    216219            (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) |
    … …  
    220223/** Returns level 1 page table entry flags.
    221224 *
    222  *  @param pt     Level 1 page table.
    223  *  @param i      Index of the entry to return.
    224  */
    225 static inline int get_pt_level1_flags(pte_t *pt, size_t i)
     225 * @param pt Level 1 page table.
     226 * @param i  Index of the entry to return.
     227 *
     228 */
     229NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
    226230{
    227231        pte_level1_t *p = &pt[i].l1;
    228 
     232       
    229233        int dt = p->descriptor_type;
    230234        int ap = p->access_permission_0;
    231 
     235       
    232236        return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
    233237            ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) |
    … …  
    241245}
    242246
    243 
    244247/** Sets flags of level 0 page table entry.
    245248 *
    246  *  @param pt     level 0 page table
    247  *  @param i      index of the entry to be changed
    248  *  @param flags  new flags
    249  */
    250 static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
     249 * @param pt    level 0 page table
     250 * @param i     index of the entry to be changed
     251 * @param flags new flags
     252 *
     253 */
     254NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
    251255{
    252256        pte_level0_t *p = &pt[i].l0;
    253 
     257       
    254258        if (flags & PAGE_NOT_PRESENT) {
    255259                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    … …  
    262266                p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
    263267                p->should_be_zero = 0;
    264     }
     268        }
    265269}
    266270
    … …  
    268272/** Sets flags of level 1 page table entry.
    269273 *
    270  *  We use same access rights for the whole page. When page is not preset we
    271  *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
    272  *  page entry, see #PAGE_VALID_ARCH).
    273  *
    274  *  @param pt     Level 1 page table.
    275  *  @param i      Index of the entry to be changed.
    276  *  @param flags  New flags.
    277  */ 
    278 static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
     274 * We use same access rights for the whole page. When page
     275 * is not preset we store 1 in acess_rigts_3 so that at least
     276 * one bit is 1 (to mark correct page entry, see #PAGE_VALID_ARCH).
     277 *
     278 * @param pt    Level 1 page table.
     279 * @param i     Index of the entry to be changed.
     280 * @param flags New flags.
     281 *
     282 */
     283NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
    279284{
    280285        pte_level1_t *p = &pt[i].l1;
    … …  
    287292                p->access_permission_3 = p->access_permission_0;
    288293        }
    289  
     294       
    290295        p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
    291 
     296       
    292297        /* default access permission */
    293298        p->access_permission_0 = p->access_permission_1 =
    294299            p->access_permission_2 = p->access_permission_3 =
    295300            PTE_AP_USER_NO_KERNEL_RW;
    296 
     301       
    297302        if (flags & PAGE_USER)  {
    298303                if (flags & PAGE_READ) {

  • kernel/arch/arm32/include/mm/tlb.h

    rc40e6ef rbd48f4c  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */

  • kernel/arch/arm32/src/asm.S

    rc40e6ef rbd48f4c  
    1 #
    2 # Copyright (c) 2007 Michal Kebrt
    3 # All rights reserved.
    4 #
    5 # Redistribution and use in source and binary forms, with or without
    6 # modification, are permitted provided that the following conditions
    7 # are met:
    8 #
    9 # - Redistributions of source code must retain the above copyright
    10 #   notice, this list of conditions and the following disclaimer.
    11 # - Redistributions in binary form must reproduce the above copyright
    12 #   notice, this list of conditions and the following disclaimer in the
    13 #   documentation and/or other materials provided with the distribution.
    14 # - The name of the author may not be used to endorse or promote products
    15 #   derived from this software without specific prior written permission.
    16 #
    17 # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
    18 # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
    19 # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    20 # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
    21 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
    22 # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    26 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    27 #
     1/*
     2 * Copyright (c) 2007 Michal Kebrt
     3 * All rights reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions
     7 * are met:
     8 *
     9 * - Redistributions of source code must retain the above copyright
     10 *   notice, this list of conditions and the following disclaimer.
     11 * - Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 * - The name of the author may not be used to endorse or promote products
     15 *   derived from this software without specific prior written permission.
     16 *
     17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27 */
    2828
    29        
    3029.text
    3130
    … …  
    3736.global memcpy_from_uspace_failover_address
    3837.global memcpy_to_uspace_failover_address
     38.global early_putchar
    3939
    4040memsetb:
    … …  
    4747memcpy_from_uspace:
    4848memcpy_to_uspace:
    49         add     r3, r1, #3
    50         bic     r3, r3, #3
    51         cmp     r1, r3
    52         stmdb   sp!, {r4, r5, lr}
    53         mov     r5, r0                  /* save dst */
    54         beq     4f
    55 1:
    56         cmp     r2, #0
    57         movne   ip, #0
    58         beq     3f
    59 2:
    60         ldrb    r3, [ip, r1]
    61         strb    r3, [ip, r0]
    62         add     ip, ip, #1
    63         cmp     ip, r2
    64         bne     2b
    65 3:
    66         mov     r0, r5
    67         ldmia   sp!, {r4, r5, pc}
    68 4:
    69         add     r3, r0, #3
    70         bic     r3, r3, #3
    71         cmp     r0, r3
    72         bne     1b
    73         movs    r4, r2, lsr #2
    74         moveq   lr, r4
    75         beq     6f
    76         mov     lr, #0
    77         mov     ip, lr
    78 5:
    79         ldr     r3, [ip, r1]
    80         add     lr, lr, #1
    81         cmp     lr, r4
    82         str     r3, [ip, r0]
    83         add     ip, ip, #4
    84         bne     5b
    85 6:
    86         ands    r4, r2, #3
    87         beq     3b
    88         mov     r3, lr, lsl #2
    89         add     r0, r3, r0
    90         add     ip, r3, r1
    91         mov     r2, #0
    92 7:
    93         ldrb    r3, [r2, ip]
    94         strb    r3, [r2, r0]
    95         add     r2, r2, #1
    96         cmp     r2, r4
    97         bne     7b
    98         b       3b
     49        add r3, r1, #3
     50        bic r3, r3, #3
     51        cmp r1, r3
     52        stmdb sp!, {r4, r5, lr}
     53        mov r5, r0 /* save dst */
     54        beq 4f
     55       
     56        1:
     57                cmp r2, #0
     58                movne ip, #0
     59                beq 3f
     60       
     61        2:
     62                ldrb r3, [ip, r1]
     63                strb r3, [ip, r0]
     64                add ip, ip, #1
     65                cmp ip, r2
     66                bne 2b
     67       
     68        3:
     69                mov r0, r5
     70                ldmia sp!, {r4, r5, pc}
     71       
     72        4:
     73                add r3, r0, #3
     74                bic r3, r3, #3
     75                cmp r0, r3
     76                bne 1b
     77                movs r4, r2, lsr #2
     78                moveq lr, r4
     79                beq 6f
     80                mov lr, #0
     81                mov ip, lr
     82       
     83        5:
     84                ldr r3, [ip, r1]
     85                add lr, lr, #1
     86                cmp lr, r4
     87                str r3, [ip, r0]
     88                add ip, ip, #4
     89                bne 5b
     90       
     91        6:
     92                ands r4, r2, #3
     93                beq 3b
     94                mov r3, lr, lsl #2
     95                add r0, r3, r0
     96                add ip, r3, r1
     97                mov r2, #0
     98       
     99        7:
     100                ldrb r3, [r2, ip]
     101                strb r3, [r2, r0]
     102                add r2, r2, #1
     103                cmp r2, r4
     104                bne 7b
     105                b 3b
    99106
    100107memcpy_from_uspace_failover_address:
    101108memcpy_to_uspace_failover_address:
    102         mov     r0, #0
    103         ldmia   sp!, {r4, r5, pc}
     109        mov r0, #0
     110        ldmia sp!, {r4, r5, pc}
     111
     112early_putchar:
     113        mov pc, lr

  • kernel/arch/arm32/src/exc_handler.S

    rc40e6ef rbd48f4c  
    9898        stmfd r13!, {r13, lr}^
    9999        stmfd r13!, {r2}
     100
     101        # Stop stack traces here
     102        mov fp, #0
     103       
    100104        b 2f
    101105
    … …  
    123127        stmfd r13!, {r2}
    1241282:
    125         # Stop stack traces here
    126         mov fp, #0
    127129.endm
    128130

  • kernel/arch/arm32/src/exception.c

    rc40e6ef rbd48f4c  
    173173 * @param istate Structure to be printed.
    174174 */
    175 void print_istate(istate_t *istate)
     175void istate_decode(istate_t *istate)
    176176{
    177         printf("istate dump:\n");
    178        
    179         printf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
     177        printf("r0 =%#0.8lx\tr1 =%#0.8lx\tr2 =%#0.8lx\tr3 =%#0.8lx\n",
    180178            istate->r0, istate->r1, istate->r2, istate->r3);
    181         printf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
     179        printf("r4 =%#0.8lx\tr5 =%#0.8lx\tr6 =%#0.8lx\tr7 =%#0.8lx\n",
    182180            istate->r4, istate->r5, istate->r6, istate->r7);
    183         printf(" r8: %x    r8: %x   r10: %x    fp: %x\n",
     181        printf("r8 =%#0.8lx\tr9 =%#0.8lx\tr10=%#0.8lx\tfp =%#0.8lx\n",
    184182            istate->r8, istate->r9, istate->r10, istate->fp);
    185         printf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
     183        printf("r12=%#0.8lx\tsp =%#0.8lx\tlr =%#0.8lx\tspsr=%#0.8lx\n",
    186184            istate->r12, istate->sp, istate->lr, istate->spsr);
    187        
    188         printf(" pc: %x\n", istate->pc);
    189 
    190         stack_trace_istate(istate);
    191185}
    192186

  • kernel/arch/arm32/src/mm/page.c

    rc40e6ef rbd48f4c  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */

  • kernel/arch/arm32/src/mm/page_fault.c

    rc40e6ef rbd48f4c  
    183183        if (ret == AS_PF_FAULT) {
    184184                fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
    185                 print_istate(istate);
    186                 printf("page fault - pc: %x, va: %x, status: %x(%x), "
    187                     "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
    188                     access);
    189                
    190                 panic("Page fault.");
     185                panic_memtrap(istate, access, badvaddr, "Page fault.");
    191186        }
    192187}
    … …  
    203198
    204199        if (ret == AS_PF_FAULT) {
    205                 printf("prefetch_abort\n");
    206                 print_istate(istate);
    207                 panic("page fault - prefetch_abort at address: %x.",
    208                     istate->pc);
     200                panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc,
     201                    "Page fault - prefetch_abort.");
    209202        }
    210203}
Note: See TracChangeset for help on using the changeset viewer.