Index: kernel/arch/sparc64/include/asm.h
===================================================================
--- kernel/arch/sparc64/include/asm.h	(revision 7c8e1e1f95d81f043e697b7dd7e6644e996009a3)
+++ kernel/arch/sparc64/include/asm.h	(revision bbfdf62eecb75fb74d785cdd587affc613b7ffe9)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -43,6 +43,7 @@
 #include <arch/stack.h>
 #include <arch/barrier.h>
-
-static inline void pio_write_8(ioport8_t *port, uint8_t v)
+#include <trace.h>
+
+NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
@@ -50,5 +51,5 @@
 }
 
-static inline void pio_write_16(ioport16_t *port, uint16_t v)
+NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
@@ -56,5 +57,5 @@
 }
 
-static inline void pio_write_32(ioport32_t *port, uint32_t v)
+NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
@@ -62,31 +63,22 @@
 }
 
-static inline uint8_t pio_read_8(ioport8_t *port)
-{
-	uint8_t rv;
-
-	rv = *port;
+NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+{
+	uint8_t rv = *port;
 	memory_barrier();
-
 	return rv;
 }
 
-static inline uint16_t pio_read_16(ioport16_t *port)
-{
-	uint16_t rv;
-
-	rv = *port;
+NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+{
+	uint16_t rv = *port;
 	memory_barrier();
-
 	return rv;
 }
 
-static inline uint32_t pio_read_32(ioport32_t *port)
-{
-	uint32_t rv;
-
-	rv = *port;
+NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+{
+	uint32_t rv = *port;
 	memory_barrier();
-
 	return rv;
 }
@@ -95,10 +87,14 @@
  *
  * @return Value of PSTATE register.
- */
-static inline uint64_t pstate_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t pstate_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%pstate, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -108,8 +104,13 @@
  *
  * @param v New value of PSTATE register.
- */
-static inline void pstate_write(uint64_t v)
-{
-	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void pstate_write(uint64_t v)
+{
+	asm volatile (
+		"wrpr %[v], %[zero], %%pstate\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -117,10 +118,14 @@
  *
  * @return Value of TICK_comapre register.
- */
-static inline uint64_t tick_compare_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tick_compare_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%tick_cmpr, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -130,8 +135,13 @@
  *
  * @param v New value of TICK_comapre register.
- */
-static inline void tick_compare_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void tick_compare_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%tick_cmpr\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -139,10 +149,14 @@
  *
  * @return Value of STICK_compare register.
- */
-static inline uint64_t stick_compare_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rd %%asr25, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t stick_compare_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%asr25, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -152,8 +166,13 @@
  *
  * @param v New value of STICK_comapre register.
- */
-static inline void stick_compare_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void stick_compare_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%asr25\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -161,10 +180,14 @@
  *
  * @return Value of TICK register.
- */
-static inline uint64_t tick_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tick_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tick, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -174,8 +197,13 @@
  *
  * @param v New value of TICK register.
- */
-static inline void tick_write(uint64_t v)
-{
-	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void tick_write(uint64_t v)
+{
+	asm volatile (
+		"wrpr %[v], %[zero], %%tick\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -183,10 +211,14 @@
  *
  * @return Value of FPRS register.
- */
-static inline uint64_t fprs_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t fprs_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%fprs, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -196,8 +228,13 @@
  *
  * @param v New value of FPRS register.
- */
-static inline void fprs_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void fprs_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%fprs\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -205,11 +242,15 @@
  *
  * @return Value of SOFTINT register.
- */
-static inline uint64_t softint_read(void)
-{
-	uint64_t v;
-
-	asm volatile ("rd %%softint, %0\n" : "=r" (v));
-
+ *
+ */
+NO_TRACE static inline uint64_t softint_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rd %%softint, %[v]\n"
+		: [v] "=r" (v)
+	);
+	
 	return v;
 }
@@ -218,8 +259,13 @@
  *
  * @param v New value of SOFTINT register.
- */
-static inline void softint_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void softint_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%softint\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -229,8 +275,13 @@
  *
  * @param v New value of CLEAR_SOFTINT register.
- */
-static inline void clear_softint_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void clear_softint_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%clear_softint\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -240,8 +291,13 @@
  *
  * @param v New value of SET_SOFTINT register.
- */
-static inline void set_softint_write(uint64_t v)
-{
-	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void set_softint_write(uint64_t v)
+{
+	asm volatile (
+		"wr %[v], %[zero], %%set_softint\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -252,10 +308,10 @@
  *
  * @return Old interrupt priority level.
- */
-static inline ipl_t interrupts_enable(void) {
+ *
+ */
+NO_TRACE static inline ipl_t interrupts_enable(void) {
 	pstate_reg_t pstate;
-	uint64_t value;
-	
-	value = pstate_read();
+	uint64_t value = pstate_read();
+	
 	pstate.value = value;
 	pstate.ie = true;
@@ -271,10 +327,10 @@
  *
  * @return Old interrupt priority level.
- */
-static inline ipl_t interrupts_disable(void) {
+ *
+ */
+NO_TRACE static inline ipl_t interrupts_disable(void) {
 	pstate_reg_t pstate;
-	uint64_t value;
-	
-	value = pstate_read();
+	uint64_t value = pstate_read();
+	
 	pstate.value = value;
 	pstate.ie = false;
@@ -289,6 +345,7 @@
  *
  * @param ipl Saved interrupt priority level.
- */
-static inline void interrupts_restore(ipl_t ipl) {
+ *
+ */
+NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
 	pstate_reg_t pstate;
 	
@@ -303,6 +360,7 @@
  *
  * @return Current interrupt priority level.
- */
-static inline ipl_t interrupts_read(void) {
+ *
+ */
+NO_TRACE static inline ipl_t interrupts_read(void) {
 	return (ipl_t) pstate_read();
 }
@@ -313,8 +371,8 @@
  *
  */
-static inline bool interrupts_disabled(void)
+NO_TRACE static inline bool interrupts_disabled(void)
 {
 	pstate_reg_t pstate;
-
+	
 	pstate.value = pstate_read();
 	return !pstate.ie;
@@ -326,10 +384,15 @@
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
- */
-static inline uintptr_t get_stack_base(void)
+ *
+ */
+NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t unbiased_sp;
 	
-	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
+	asm volatile (
+		"add %%sp, %[stack_bias], %[unbiased_sp]\n"
+		: [unbiased_sp] "=r" (unbiased_sp)
+		: [stack_bias] "i" (STACK_BIAS)
+	);
 	
 	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
@@ -339,10 +402,14 @@
  *
  * @return Value of VER register.
- */
-static inline uint64_t ver_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t ver_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%ver, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -352,10 +419,14 @@
  *
  * @return Current value in TPC.
- */
-static inline uint64_t tpc_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tpc_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tpc, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -365,10 +436,14 @@
  *
  * @return Current value in TL.
- */
-static inline uint64_t tl_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tl_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tl, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -378,10 +453,14 @@
  *
  * @return Current value in TBA.
- */
-static inline uint64_t tba_read(void)
-{
-	uint64_t v;
-	
-	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
+ *
+ */
+NO_TRACE static inline uint64_t tba_read(void)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"rdpr %%tba, %[v]\n"
+		: [v] "=r" (v)
+	);
 	
 	return v;
@@ -391,8 +470,13 @@
  *
  * @param v New value of TBA.
- */
-static inline void tba_write(uint64_t v)
-{
-	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
+ *
+ */
+NO_TRACE static inline void tba_write(uint64_t v)
+{
+	asm volatile (
+		"wrpr %[v], %[zero], %%tba\n"
+		:: [v] "r" (v),
+		   [zero] "i" (0)
+	);
 }
 
@@ -400,13 +484,20 @@
  *
  * @param asi ASI determining the alternate space.
- * @param va Virtual address within the ASI.
- *
- * @return Value read from the virtual address in the specified address space.
- */
-static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
-{
-	uint64_t v;
-	
-	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
+ * @param va  Virtual address within the ASI.
+ *
+ * @return Value read from the virtual address in
+ *         the specified address space.
+ *
+ */
+NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
+{
+	uint64_t v;
+	
+	asm volatile (
+		"ldxa [%[va]] %[asi], %[v]\n"
+		: [v] "=r" (v)
+		: [va] "r" (va),
+		  [asi] "i" ((unsigned int) asi)
+	);
 	
 	return v;
@@ -416,14 +507,21 @@
  *
  * @param asi ASI determining the alternate space.
- * @param va Virtual address within the ASI.
- * @param v Value to be written.
- */
-static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
-{
-	asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
+ * @param va  Virtual address within the ASI.
+ * @param v   Value to be written.
+ *
+ */
+NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
+{
+	asm volatile (
+		"stxa %[v], [%[va]] %[asi]\n"
+		:: [v] "r" (v),
+		   [va] "r" (va),
+		   [asi] "i" ((unsigned int) asi)
+		: "memory"
+	);
 }
 
 /** Flush all valid register windows to memory. */
-static inline void flushw(void)
+NO_TRACE static inline void flushw(void)
 {
 	asm volatile ("flushw\n");
@@ -431,5 +529,5 @@
 
 /** Switch to nucleus by setting TL to 1. */
-static inline void nucleus_enter(void)
+NO_TRACE static inline void nucleus_enter(void)
 {
 	asm volatile ("wrpr %g0, 1, %tl\n");
@@ -437,5 +535,5 @@
 
 /** Switch from nucleus by setting TL to 0. */
-static inline void nucleus_leave(void)
+NO_TRACE static inline void nucleus_leave(void)
 {
 	asm volatile ("wrpr %g0, %g0, %tl\n");
