Changeset b994a60 in mainline for arch/ia64/include


Ignore:
Timestamp:
2006-03-09T12:44:27Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
901122b
Parents:
cd373bb
Message:

ia64 work.
Changes to make userspace work (kernel part).
Use ski.conf from contrib directory to run Ski.

There is actually no appropriate syscall handler yet.

Location:
arch/ia64/include
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • arch/ia64/include/asm.h

    rcd373bb rb994a60  
    4949}
    5050
     51/** Return Processor State Register.
     52 *
     53 * @return PSR.
     54 */
     55static inline __u64 psr_read(void)
     56{
     57        __u64 v;
     58       
     59        __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
     60       
     61        return v;
     62}
     63
    5164/** Read IVA (Interruption Vector Address).
    5265 *
    … …  
    233246static inline ipl_t interrupts_read(void)
    234247{
    235         __u64 v;
    236        
    237         __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
    238        
    239         return (ipl_t) v;
     248        return (ipl_t) psr_read();
    240249}
    241250
    … …  
    250259extern void asm_delay_loop(__u32 t);
    251260
     261extern void switch_to_userspace(__address entry, __address sp, __address bsp, __u64 ipsr, __u64 rsc);
     262
    252263#endif

  • arch/ia64/include/context.h

    rcd373bb rb994a60  
    3131
    3232#include <arch/types.h>
     33#include <arch/register.h>
    3334#include <typedefs.h>
    3435#include <align.h>
    … …  
    4243 */
    4344#define SP_DELTA        (0+ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT))
    44 
    45 #define PFM_MASK        (~0x3fffffffff)
    4645
    4746#ifdef context_set

  • arch/ia64/include/mm/as.h

    rcd373bb rb994a60  
    3232#include <arch/types.h>
    3333
    34 #define KERNEL_ADDRESS_SPACE_START_ARCH         (__address) 0x8000000000000000
    35 #define KERNEL_ADDRESS_SPACE_END_ARCH           (__address) 0xffffffffffffffff
    36 #define USER_ADDRESS_SPACE_START_ARCH           (__address) 0x0000000000000000
    37 #define USER_ADDRESS_SPACE_END_ARCH             (__address) 0x7fffffffffffffff
     34#define KERNEL_ADDRESS_SPACE_START_ARCH         (__address) 0xe000000000000000ULL
     35#define KERNEL_ADDRESS_SPACE_END_ARCH           (__address) 0xffffffffffffffffULL
     36#define USER_ADDRESS_SPACE_START_ARCH           (__address) 0x0000000000000000ULL
     37#define USER_ADDRESS_SPACE_END_ARCH             (__address) 0xdfffffffffffffffULL
    3838
    39 #define UTEXT_ADDRESS_ARCH      0x0000000000001000
    40 #define USTACK_ADDRESS_ARCH     (0x7fffffffffffffff-(PAGE_SIZE-1))
    41 #define UDATA_ADDRESS_ARCH      0x0000000001001000
     39#define UTEXT_ADDRESS_ARCH      0x0000000000010000ULL
     40#define USTACK_ADDRESS_ARCH     0x0000000ff0000000ULL
     41#define UDATA_ADDRESS_ARCH      0x0000000001010000ULL
    4242
    4343extern void as_arch_init(void);

  • arch/ia64/include/register.h

    rcd373bb rb994a60  
    3030#define __ia64_REGISTER_H__
    3131
    32 #ifndef __ASM__
    33 #include <arch/types.h>
    34 #endif
    35 
    3632#define CR_IVR_MASK     0xf
    3733#define PSR_IC_MASK     0x2000
    … …  
    4541#define PSR_CPL_SHIFT           32
    4642#define PSR_CPL_MASK_SHIFTED    3
     43
     44#define PFM_MASK        (~0x3fffffffff)
     45
     46#define RSC_MODE_MASK   3
     47#define RSC_PL_MASK     12
    4748
    4849/** Application registers. */
    … …  
    121122
    122123#ifndef __ASM__
     124
     125#include <arch/types.h>
     126
     127/** Processor Status Register. */
     128union psr {
     129        __u64 value;
     130        struct {
     131                unsigned : 1;
     132                unsigned be : 1;        /**< Big-Endian data accesses. */
     133                unsigned up : 1;        /**< User Performance monitor enable. */
     134                unsigned ac : 1;        /**< Alignment Check. */
     135                unsigned mfl : 1;       /**< Lower floating-point register written. */
     136                unsigned mfh : 1;       /**< Upper floating-point register written. */
     137                unsigned : 7;
     138                unsigned ic : 1;        /**< Interruption Collection. */
     139                unsigned i : 1;         /**< Interrupt Bit. */
     140                unsigned pk : 1;        /**< Protection Key enable. */
     141                unsigned : 1;
     142                unsigned dt : 1;        /**< Data address Translation. */
     143                unsigned dfl : 1;       /**< Disabled Floating-point Low register set. */
     144                unsigned dfh : 1;       /**< Disabled Floating-point High register set. */
     145                unsigned sp : 1;        /**< Secure Performance monitors. */
     146                unsigned pp : 1;        /**< Privileged Performance monitor enable. */
     147                unsigned di : 1;        /**< Disable Instruction set transition. */
     148                unsigned si : 1;        /**< Secure Interval timer. */
     149                unsigned db : 1;        /**< Debug Breakpoint fault. */
     150                unsigned lp : 1;        /**< Lower Privilege transfer trap. */
     151                unsigned tb : 1;        /**< Taken Branch trap. */
     152                unsigned rt : 1;        /**< Register Stack Translation. */
     153                unsigned : 4;
     154                unsigned cpl : 2;       /**< Current Privilege Level. */
     155                unsigned is : 1;        /**< Instruction Set. */
     156                unsigned mc : 1;        /**< Machine Check abort mask. */
     157                unsigned it : 1;        /**< Instruction address Translation. */
     158                unsigned id : 1;        /**< Instruction Debug fault disable. */
     159                unsigned da : 1;        /**< Disable Data Access and Dirty-bit faults. */
     160                unsigned dd : 1;        /**< Data Debug fault disable. */
     161                unsigned ss : 1;        /**< Single Step enable. */
     162                unsigned ri : 2;        /**< Restart Instruction. */
     163                unsigned ed : 1;        /**< Exception Deferral. */
     164                unsigned bn : 1;        /**< Register Bank. */
     165                unsigned ia : 1;        /**< Disable Instruction Access-bit faults. */
     166        } __attribute__ ((packed));
     167};
     168typedef union psr psr_t;
     169
     170/** Register Stack Configuration Register */
     171union rsc {
     172        __u64 value;
     173        struct {
     174                unsigned mode : 2;
     175                unsigned pl : 2;        /**< Privilege Level. */
     176                unsigned be : 1;        /**< Big-endian. */
     177                unsigned : 11;
     178                unsigned loadrs : 14;
     179        } __attribute__ ((packed));
     180};
     181typedef union rsc rsc_t;
     182
    123183/** External Interrupt Vector Register */
    124184union cr_ivr {
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