Changeset b52da8d7 in mainline for arch


Ignore:
Timestamp:
2005-08-29T11:57:26Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c245372b
Parents:
229d5fc1
Message:

Add some comments to IA-32 src/boot/boot.S and src/smp.S.

Make the boot stack start on page boundary.
This is required by get_stack_base().

Define 'THE' macro.

Implement preemption_disable() and preemption_enable().

Add memory barrier macros.
IA-32 macros need support for older processors.
Non IA-32 macros are dummy.

Reduction of many #include paths.

Location:
arch
Files:
11 edited

Legend:

Unmodified
Added
Removed

  • arch/amd64/include/barrier.h

    r229d5fc1 rb52da8d7  
    3333#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    3434
     35#define memory_barrier()
     36#define read_barrier()
     37#define write_barrier()
     38
    3539#endif

  • arch/ia32/include/asm.h

    r229d5fc1 rb52da8d7  
    3232#include <arch/types.h>
    3333#include <typedefs.h>
    34 #include <mm/page.h>
     34#include <config.h>
    3535#include <synch/spinlock.h>
    3636#include <arch/boot/memmap.h>

  • arch/ia32/include/barrier.h

    r229d5fc1 rb52da8d7  
    4444#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    4545
     46#define memory_barrier()        __asm__ volatile ("mfence\n" ::: "memory")
     47#define read_barrier()          __asm__ volatile ("sfence\n" ::: "memory")
     48#define write_barrier()         __asm__ volatile ("lfence\n" ::: "memory")
     49
    4650#endif

  • arch/ia32/src/boot/boot.S

    r229d5fc1 rb52da8d7  
    4848        call memmap_arch_init
    4949       
    50         lgdt gdtr
     50        lgdt gdtr                       # initialize Global Descriptor Table register
     51        lidt idtr                       # initialize Interrupt Descriptor Table register
     52       
    5153        movl %cr0,%eax
    5254        orl $0x1,%eax
    53         movl %eax,%cr0
     55        movl %eax,%cr0                  # switch to protected mode
    5456        jmpl $8,$meeting_point
    5557meeting_point:
    … …  
    6365        movw %ax,%ss
    6466
    65         lidt idtr
    66 
    67         call map_kernel
     67        call map_kernel                 # map kernel and turn paging on
    6868
    6969        movl $_hardcoded_ktext_size, hardcoded_ktext_size
    … …  
    9595        movl %eax, %cr3
    9696       
    97         # turn on paging
     97        # turn paging on
    9898        movl %cr0, %ebx
    9999        orl $(1<<31), %ebx

  • arch/ia32/src/mm/frame.c

    r229d5fc1 rb52da8d7  
    3535#include <print.h>
    3636
    37 /*
    38  * TODO: use the memory map obtained from BIOS
    39  */
    4037void frame_arch_init(void)
    4138{

  • arch/ia32/src/smp/ap.S

    r229d5fc1 rb52da8d7  
    5151        movw %ax,%ds
    5252
    53         lgdt gdtr
     53        lgdt gdtr                       # initialize Global Descriptor Table register
     54        lidt idtr                       # initialize Interrupt Descriptor Table register
     55       
    5456        movl %cr0,%eax
    5557        orl $1,%eax
    56         movl %eax,%cr0
     58        movl %eax,%cr0                  # switch to protected mode
    5759        jmpl $KTEXT,$jump_to_kernel
    5860jump_to_kernel:
    … …  
    6668        subl $0x80000000,%esp           # KA2PA(ctx.sp)
    6769
    68         lidt idtr
    69 
    70         call map_kernel
     70        call map_kernel                 # map kernel and turn paging on
    7171
    7272        jmpl $KTEXT,$main_ap

  • arch/ia64/include/barrier.h

    r229d5fc1 rb52da8d7  
    3636#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    3737
     38#define memory_barrier()
     39#define read_barrier()
     40#define write_barrier()
     41
    3842#endif

  • arch/mips/include/barrier.h

    r229d5fc1 rb52da8d7  
    3636#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    3737
     38#define memory_barrier()
     39#define read_barrier()
     40#define write_barrier()
     41
    3842#endif

  • arch/mips/include/cpu.h

    r229d5fc1 rb52da8d7  
    3030#define __mips_CPU_H__
    3131
    32 #include <typedefs.h>
    33 
    3432#define CPU_ID_ARCH     0
    3533

  • arch/mips/include/mm/page.h

    r229d5fc1 rb52da8d7  
    3434#include <arch/mm/frame.h>
    3535#include <arch/types.h>
    36 #include <arch.h>
    3736
    3837#define PAGE_SIZE       FRAME_SIZE

  • arch/ppc/include/barrier.h

    r229d5fc1 rb52da8d7  
    3333#define CS_LEAVE_BARRIER()      __asm__ volatile ("" ::: "memory")
    3434
     35#define memory_barrier()
     36#define read_barrier()
     37#define write_barrier()
     38
    3539#endif
Note: See TracChangeset for help on using the changeset viewer.